Double-diffused Metal Oxide Semiconductor Field-effect Transistor Research Articles

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET.

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

Temperature Reliability Investigation for a 400 W Solid-State Power Amplifier under High and Cold Conditions

In order to study the temperature reliability of high-power amplifiers under high cand cold conditions, a 400 W solid-state power amplifier was taken as an example to explore the variation in its performance. The test results showed that its output power, gain, and power-added efficiency increased with the increase in temperature at a fixed frequency. Under a fixed input power, Pout and gain both showed different trends with the rising temperature. Within the frequency band of 2–10 MHz, the higher the temperature, the better the output power and gain. However, within the frequency range of 10–30 MHz, the higher the temperature, the worse the performance. Moreover, with the increasing temperature, its power-added efficiency, the second harmonic and the third harmonic also showed a decreasing trend. Detailed analysis showed that the degradation and inversion of performance parameters are closely related to the zero temperature coefficient and self-heating effect of the lateral double-diffused metal–oxide–semiconductor field-effect transistor. Meanwhile, it is also affected by the circuit structure and thermal design of the PA. In order to ensure stable performance in different environments, performance degradation can be improved by hardware compensation. Therefore, analyzing the working parameters at different temperatures for high-power PAs is the key to achieving temperature control and ensuring their long-term stability and reliability. This can provide relatively accurate reference data for subsequent heat dissipation optimization, greatly improve design efficiency, and even shorten the development cycle and reduce costs.

Charge deposition analysis of heavy-ion-induced single-event burnout in low-voltage power VDMOSFET

The heavy-ion-induced single-event burnout (SEB) risk in power MOSFETs (metal-oxide-semiconductor field-effect transistors) can be assessed in ground facilities, although it is costly and time-demanding. For this reason, there have been few experimental studies dedicated to investigate the relevant parameter related to the description of ion-induced SEB phenomenon. In this work the heavy-ion-induced SEB in a low-voltage power VDMOSFET (vertical double-diffused MOSFET) is studied using several ion-energy combinations. A self-consistent statistical analysis is carried out in order to elucidate the relationship between charge deposition and SEB triggering. Experimental data is compared to a predictive model from the literature for SEE (single-event effect) worst-case prediction in power MOSFETs, supporting for the first time its relevance to the worst-case prediction in the SEB mechanism.

Analysis of SEGR in Silicon Planar Gate Super-Junction Power MOSFETs

This article compares and analyzes the single-event gate rupture (SEGR) response of silicon planar gate super-junction (SJ) power metal oxide semiconductor field effect transistors (MOSFETs) and vertical double diffused power MOSFETs (VDMOSs). When an incident heavy-ion strike is perpendicular to the gate oxide, the SEGR tolerances of SJ power MOSFETs (SJMOSs) and VDMOSs are similar. But, for heavy-ion strikes that are at different angles, SJMOS has better SEGR tolerance than VDMOS. This improved performance of SJMOS is due to the presence of an additional horizontal electric field component in SJMOS devices. This is validated using the experimental data and simulation results in this article.

Determination of Power MOSFET’s Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes

In this article, we aim to investigate the gate oxide degradation of power MOSFETs through oxide capacitance. We focus on modeling the oxide capacitance variation as a function of several stress levels and time intervals. The experimental procedure is carried out by means of commercial n-channel vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOSFETs) that have maximum voltage and current ratings as 200 V and 5.2A, respectively. We calculate the oxide capacitance using measurable reverse capacitance that is equal to gate–drain capacitance. The turn-around point is determined at each stress level. We observe that the oxide capacitance shows a nonlinear variation due to the stress time and level. The variation is divided into two regions for the model. The modeling procedure starts with the mathematical fitting. The equations are obtained by using curve fitting methods. The circuit model is designed via SPICE Simulation by using these equations. We also consider the turn-around points for the circuit design. The simulation and experimental results have good compatibility. We achieve 92.3% and 90.8% similarity on average for first and second region of the variation, respectively.

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit* *Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

Investigating the Failure Mechanism of Short-Circuit Tests in 1.2-kV SiC JBS-Integrated MOSFETs

In this article, the failure mechanism of a 1.2-kV monolithic junction barrier-controlled Schottky diode integrated silicon carbide metal–oxide–semiconductor field-effect transistor (JMOS) under short-circuit (SC) tests has been investigated by an experimental validation and simulation analysis. As a new type of device, JMOS has superior performance and chip area efficiency. However, the SC ruggedness of the JMOS needs further investigation. When comparing vertical double-diffused metal–oxide–semiconductor field-effect transistor (VDMOS) and JMOS devices in the SC test study, the leakage current of the JMOS is much higher than that of a common VDMOS. During the SC test, the JMOS drain current cannot be successfully suppressed after gate turn-off, and the thermionic emission current due to heat generation in the Schottky barrier diode (SBD) region continues flowing into the n-drift region. The SBD thermionic emission current is rapidly increased by the increasing lattice temperature, which can reach over 1600 K. Eventually, the JMOS undergoes thermal runaway due to positive electrothermal feedback. A mechanistic study was set up to analyze the relationship between the SC limit and the leakage current in the SBD region of the heated materials. Finally, the key to improve the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.

PSJ LDMOS with a VK dielectric layer

A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable- k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low- k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance ( R on,sp ). Furthermore, according to an enhanced dielectric layer field, low- k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate**Project supported by the National Natural Science Foundation of China (Grant No. 61464003) and the Guangxi Natural Science Foundation, China (Grant Nos. 2015GXNSFAA139300 and 2018JJA170010).

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 mΩ·cm2 to 23.24 mΩ·cm2 and the Baliga’s figure of merit (FOM) of is 9.07 MW/cm2.

Modeling and Evaluation of Stacking Fault Expansion Velocity in Body Diodes of 3.3 kV SiC MOSFET

We evaluated the stacking fault (SF) expansion velocity by electrical characteristics and estimated the screening test condition, which is a stress test with current to eliminate 4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) whose forward voltage would be degraded during bipolar operation. First, double-diffused MOSFETs were fabricated, and forward current stress tests were applied to the body diodes in SiC MOSFETs. Their electrical characteristics were measured before and after forward voltage degradation at several junction temperatures. Second, to clarify the SF expansion sequence from a basal plane dislocation in the SiC epitaxial layer, continuous irradiation by an Hg lamp and photoluminescence (PL) observation were executed. Then, we present a model to explain the characteristics of the forward voltage degradation by a combination of the results of electrical measurement and PL observation. The characteristics calculated by using the presented model were in good agreement with the measured ones. Finally, forward current stress tests were applied to the body diodes in SiC MOSFETs with various conditions, and the SF expansion velocity was evaluated by calculation. These results indicate that the SF expansion velocity increases with forward current density and junction temperature. The estimated activation energy for the SF expansion velocity in the direction is estimated to be 0.24 eV at a forward current density of 120 A/cm2.

Updated structure of vertical double-diffused MOSFETs for irradiation hardening against single events

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal–oxide–semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.

High electric field stress model of n-channel VDMOSFET based on artificial neural network

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

Improvement of Deep-Trench LDMOS With Variation Vertical Doping for Charge-Balance Super-Junction

A design concept of variation vertical doping is proposed to upgrade the deep-trench lateral double-diffused metal–oxide–semiconductor field-effect transistor. Due to the proposal, a drift region in the form of charge-balance super-junction is first gained in such a device. Hence, the relationship between the breakdown voltage and the specific on-resistance is significantly improved. Numerical simulations demonstrate that the proposal is valid to increase the theoretical limit of the figure of merit to be about 44.9 MW/cm $^{\textsf {2}}$ , more than twice of that of the prior art. Besides, a feasible realization method is presented and studied.

A review of pulsed NBTI in P-channel power VDMOSFETs

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide-semiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

PSOI pLDMOS with n‐buried layer

Partial-silicon (Si)-on-insulator p-channel lateral double-diffused metal–oxide–semiconductor field-effect transistor with n-buried layer (NBL PSOI pLDMOS) is proposed. One feature of the device is an Si window under the drain offers a heat conduction path to alleviate the self-heating effect. Meanwhile, a fully depleted NBL on the bottom surface of the Si layer provides a large amount of ionised donors to enhance the electric field of the buried oxide (BOX) layer. The NBL can prevent the substrate leakage phenomenon of the PSOI pLDMOS. There is a triple reduced surface field structure in the p-drift region. Some equipotential lines spread into the p-substrate through the Si window. Furthermore, the assistant depletion caused by the NBL increases the p-drift region concentration, which achieves a lower specific on-resistance (R on,sp). With 20 µm p-drift region length and 1 µm BOX thickness, the NBL PSOI pLDMOS obtains a higher breakdown voltage (BV) of 289 V, which is increased by 88.9 and 43.8% compared with the Con SOI and NBL SOI pLDMOS, respectively. The R on,sp is decreased by 82.3 and 17.2%, respectively. The figure of merit (FOM = BV2/R on,sp) is 1.65 MW cm−2. A lower maximum surface temperature of 312.3 K is obtained.

SOI LDMOSFET with Up and Down Extended Stepped Drift Region

To increase the breakdown voltage and decrease the ON resistance, a silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in which the drift region extends to the up and down oxides in a step shape is proposed. This up and down extended stepped drift SOI (UDESD-SOI) structure demonstrates a modified lateral electric field distribution with additional peaks as well as a decrease of the usual peaks near the drain and gate. Two-dimensional (2D) simulations were used to compare the characteristics of the proposed UDESD-SOI structure with those of other structures, viz. down extended stepped drift SOI (DESD-SOI), up extended stepped drift SOI (UESD-SOI), and conventional SOI (C-SOI). Under the same conditions, the breakdown voltage of the UDESD-SOI structure was nearly 35%, 117%, and 318% higher compared with the DESD-SOI, UESD-SOI, and C-SOI structure, respectively. To determine the optimum parameters for the UDESD-SOI structure leading to the highest breakdown voltage, a comparative study was performed to investigate the effect of the doping concentration in the drift region, buried oxide (BOX) thickness, and thickness of up and down extended steps (T 1 and T 2, respectively). In addition, the drain current (ON resistance) of the UDESD-SOI structure was found to be 13%, 43%, and 229% higher (16%, 65%, and 257% lower) than the values for the DESD-SOI, UESD-SOI, and C-SOI structure, respectively.

Dimension Effect on Breakdown Voltage of Partial SOI LDMOS

Dimension effect on breakdown voltage (BV) of lateral double-diffused metal-oxide–semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is comprehensively studied. The maximum BV (BVmax) is examined under various settings of the device length ${L}$ and the active silicon film thickness ${t}$ . It is shown that there exists an optimal pair of ( ${L}$ , ${t}$ ) for PSOI at which the highest BV can be achieved. The ratio of ${L}$ / ${t}$ is better chosen between 5 and 7 for the device designs, in particular, $L/t={\mathrm{ 6}}$ can be considered as the optimal one theoretically. Moreover, impacts of the silicon window length $L_{w}$ and the drift doping concentration $N_{dr}$ on the BV, the on-resistance ( $R_{\mathrm{ on}}$ ) and the figure-of-merit ( $=\!{\mathrm{ BV}}^{2}/R_{\mathrm{ on}}$ ) are also carefully studied.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance**Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Design of Super-junction TMOSFET with Embedded Temperature Sensor

Super-junction trench MOSFET (SJ TMOSFET) devices are well known for lower specific on-resistance and high breakdown voltage (BV). For a conventional power MOSFET (metal-oxide semiconductor field-effect transistor) such as trench double-diffused MOSFET (TDMOSFET), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a SJ TMOSFET structure is suggested, but sensing the temperature distribution of TMOSFET is very important in the application since heat is generated in the junction area affecting TMOSFET. In this paper, analyzing the temperature characteristics for different number bonding for SJ TMOSFET with an embedded temperature sensor is carried out after designing the diode temperature sensor at the surface of SJ TMOSFET for the class of 100 V and 100 A for a BLDC motor.