Double-balanced Mixer Research Articles

A Low-Power W-Band SiGe-HBT Double-Balanced Up-Conversion Mixer With an Integrated Second-Order IF Low-Pass Filter

A Low-Power W-Band SiGe-HBT Double-Balanced Up-Conversion Mixer With an Integrated Second-Order IF Low-Pass Filter

A 10 bits 26 mW 0.08 mm[formula omitted] digital RF-DAC for sub-GHz IoTs

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ−Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply.

Modified Broadband Ruthroff-Type Transmission Line Transformer Balun for Isolation-Enhanced Passive Mixer Design.

Generalized broadband operation facilitates multifunction or multiband highly integrated applications, such as modern transceiver systems, where ultra-wideband bidirectional passive mixers are favored to avoid a complex up/down-conversion scheme. In this paper, a modified Ruthroff-type transmission line transformer (TLT) balun is presented to enhance the isolation of the mixer from the local oscillator (LO) to the radio frequency (RF). Compared to the conventional methods, the proposed Ruthroff-type architecture adopts a combination of shunt capacitors and parallel coupled lines to improve the return loss at the LO port, thus effectively avoiding the area consumption for the diode-to-balun impedance transformation while simultaneously providing a suitable point for IF extraction. In addition, a parallel compensation technique consisting of an inductor and resistor is applied to the RF balun to significantly improve the amplitude/phase balance performance over a wide bandwidth. Benefiting from the aforementioned operations, an isolation-enhanced 8-30 GHz passive double-balanced mixer is designed as a proof-of-principle demonstration via 0.15-micrometer GaAs p-HEMT technology. It exhibits ultra-broadband performance with 7 dB average conversion loss and 50 dB LO-to-RF isolation under 15 dBm LO power. The monolithic microwave integrated circuit area is 0.96 × 1.68 mm2 including all pads.

A wideband low power RF Receiver Front-End for Internet-of-Things applications

This paper presents a broadband RF receiver front-end circuit that offers advantages in both area and power consumption. The design features an innovative dual-path noise-canceling Low-Noise Amplifier (LNA) circuit, achieving impedance matching and balun functionality without the need for on-chip inductors. The RF receiver front-end circuit comprises a I and Q doublebalanced quadrature passive mixers and an 25% duty-cycle LO generator. The circuit’s broadband characteristics enable it to operate across a wide range of frequency bands. It is implemented using a 65 nm CMOS process. The core circuit, including both RF and baseband signal paths, consumes a mere 12 mW of power. Test results demonstrate that the RF receiver front-end circuit achieves a conversion gain of 35–40 dB, a noise figure (NF) below 4.8 dB, and a minimum third-order intercept point (IIP3) exceeding −6.8 dBm over the 0.1–3.1 GHz frequency range. The chip’s overall footprint is compact at 0.9 mm2, with the entire RF signal path powered by a 1 V supply, offering clear advantages in terms of compactness and low power consumption.

A 55 nm CMOS RF Transmitter Front-End with an Active Mixer and a Class-E Power Amplifier for 433 MHz ISM Band Applications

In order to meet the increasing demands of wireless communication for ISM bands, a 433 MHz transmitter RF front-end is designed using a 55 nm low-power CMOS technology. The circuits consist of an active mixer, a driver amplifier and a class-E power amplifier (PA). A double-balanced Gilbert active mixer is designed to realize binary phase-shift keying (BPSK) modulation. The driver is used to preamplify the modulated RF signals. The class-E PA adopts a parallel four-branch cascode structure to control the output power level. The load network of the PA is implemented through an off-chip circuit, in which a finite DC-feed inductance load network is selected to reduce the power loss. The mixer and driver are designed with a 1.2 V supply voltage, while the PA is operated at a 1.8 V supply voltage. The area of the chip is 0.206 mm × 0.089 mm, and the measured results show that it achieves a maximum output power of 2.7 dBm, with a total power consumption of 6.72 mW. At a drain efficiency (DE) of 34.5%, an S22 less than −10 dB over the frequency ranges from 393.79 MHz to 455.70 MHz can be measured for the PA. With 192 kbps BPSK data modulated at 433 MHz, the measured EVM is about 0.83% rms.

The Design of a 1-6 GHz Broadband Double-Balanced Mixer.

This brief proposes a 1-6 GHz broadband double-balanced mixer. On the basis of the standard Marchand balun mixer, two techniques to enhance the performance of the mixer are proposed. Firstly, by loading capacitors, the amplitude and phase imbalance of the balun at high frequencies are improved, thereby expanding the relative bandwidth of the mixer by 0.1. Secondly, by cascading a first-order LC filter at the intermediate-frequency (IF) port, the leakage of radio frequency (RF) and local oscillator (LO) signals at the IF port is reduced by approximately 8 dB and 7 dB, respectively. This brief analyzes the various parameters that affect balun indicators and designs a broadband balun with a double-layer spiral line structure. As a result of these technologies, a 1-6 GHz double-balanced mixer is realized. The chip area is 1.13 mm × 0.95 mm, and the isolation between the IF port and the RF port is 34 dB and yields 13.5 dBm input power at 1 dB compression point (IP1 dB). The chip is fabricated via the GaAs pHEMT process.

A Machine Learning Integrated 5.8-GHz Continuous-Wave Radar for Honeybee Monitoring and Behavior Classification

A 5.8-GHz continuous-wave (CW) radar was developed and integrated on a compact printed circuit board (PCB) for near-hive monitoring of honeybees. It supported noninvasive detection of free-flying honeybees at 2 m and micro-Doppler extraction of bee wingbeat signatures at a closer range using both a double-balanced mixer and an in-phase/quadrature (IQ) mixer. An original technique combining full-wave simulations and Doppler-radar monitoring of pendulum motion was used for: radar calibration through spherical targets of different material and size; precise extraction of bee radar cross section (RCS) at 5.8 GHz; and estimation of detection range enhancement through partial silver coating of targets. Finally, the CW radar was integrated with machine learning (ML) to allow automated classification of incoming, outgoing, and hovering honeybees. Different ML approaches were tested, where the highest accuracy of 93.37% was found in ternary classification via support vector machine acting on line spectral frequencies.

An 18–50-GHz Double-Balanced GaAs Mixer Using Novel Ultrawideband Balun

In this letter, a novel multiconductor coupled line (MCL) balun is presented for the implementation of a wideband double balanced mixer (DBM). The proposed balun utilizes an artificial transmission line (ATL) (composed of periodical shunt stubs), and manages to shorten the length by 65.1% compared with the three-line balun. Besides, in order to provide a point for intermediate frequency (IF) extraction, two sections of coupled lines are exclusively added behind local oscillator (LO) balun. And this structure also transmits LO signals to the diodes for mixing. Through the aforementioned operations, a compact balun and an 18–50 GHz mixer in 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m GaAs pseudomorphic high electron mobility transistor (p-HEMT) process are designed. The measured results show that within the operation frequency, the phase and amplitude difference of the balun are lower than 3.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> and 1.1 dB, respectively. The mixer dB conversion loss (CL) and 33 dB LO-to-RF isolation under 15 dBm LO power. The monolithic microwave integrated circuit (MMIC) area is 0.96 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1.68 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , including all pads.

An apparatus for probing multipactor in X-band waveguide components

Rectangular waveguides are susceptible to avalanche-style breakdown via the multipactor phenomenon. The growth in secondary electron density produced via multipactor can damage and destroy RF components. A pulse-adjustable, hard-switched modulator powering an X-band magnetron was utilized to drive a modular experimental setup that enables testing different surface geometries and coatings. Power measurements, taken via diodes, and phase measurements, facilitated via a double-balanced mixer, were integrated into the overall apparatus enabling multipactor detection with high sensitivity and nanosecond temporal resolution. The utilized 150 kW peak microwave source with 2.5 μs pulse width and 100Hz repetition frequency allows for threshold testing without the need for initial electron seeding. This paper includes the initial results of surface conditioning of the test multipactor gap via electron bombardment.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

A 39-GHz High Image-Rejection Up-Conversion Mixer in 65-nm CMOS for 5G Communication

This brief presents an up-conversion mixer with high image rejection ratio (IRR) for 5G mmWave communication. To achieve broadband IRR at mmWave frequency with high area efficiency, a current-mode second-order tunable notch filter embedded in a cascode radio frequency (RF) buffer is proposed to realize tracking of the pole and zero frequencies with the switch capacitor array. To address the local oscillator (LO) leakage and even-harmonic distortion, a double-balanced passive mixer is adopted. For better isolation and lower insertion loss, a capacitor-inductor-capacitor (C-L-C) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\pi }$ </tex-math></inline-formula> -type impedance network is introduced in the mmWave T/R switch, realizing the equivalent lumped quarter wave transmission line with high area efficiency. Fabricated in a 65-nm CMOS process, the up-conversion mixer consumes 48.6 mW from a 1.2-V supply. Within the 3-dB bandwidth from 36 to 40.6 GHz, the mixer has a peak conversion gain of 0 dB, and its measured output 1-dB gain compression point (OP1dB) varies from −3 to −1.8 dBm. With the proposed tunable notch filter, the up-conversion mixer achieves a measured IRR of more than 53 dBc from 36 to 40.6 GHz, with a peak value of 58 dBc at 38.2 GHz.

Noise-Reduced and PVT-Robust Double-Balanced CMOS Mixer Using Common-Mode Feedback

Noise-Reduced and PVT-Robust Double-Balanced CMOS Mixer Using Common-Mode Feedback

An ISM-band direct down-conversion double-balanced mixer for biomedical applications

An ISM-band direct down-conversion double-balanced mixer for biomedical applications

Coupling Effects Analysis and Suppression in a Highly Integrated Ka-Band Receiver Front-End MMIC for a Passive Millimeter-Wave Imager System

This paper presents the coupling effects analysis and suppression of a highly integrated receiver front-end MMIC for a passive millimeter-wave imager system. The receiver MMIC consists of a low-noise amplifier, double-balanced image-reject mixer, frequency quadrupler, and analog phase shifter. In order to integrate these devices into a compact single chip without affecting the core performance, coupling problems need to be solved. We analyze the influence of coupling effects on the image rejection ratio, and propose corresponding solutions for three different coupling paths. (1) The coupling in the LO-RF path of the mixer is solved by designing a double-balanced mixer with high isolation characteristics. (2) The coupling between the LO chain and the LNA from space and dielectric is suppressed by optimizing the two main transmission lines spacing and adding isolation vias. (3) The coupling caused by the line crossing is restrained by designing a differential line crossover structure. The design and implementation of the MMIC are based on 0.15 µm GaAs pHEMT process. The receiver chip has 6.1~8.7 dB conversion gain in 32~36 GHz, less than 3.5 dB of noise figure, and more than 35 dB of image rejection ratio. The measurement results show that the receiver MMIC is especially suitable for high-sensitivity passive millimeter-wave imaging systems.

A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time, τ , for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-&lt;i&gt;g&lt;/i&gt;&lt;sub&gt;m&lt;/sub&gt; differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm&lt;sup&gt;2&lt;/sup&gt;, and power consumption is only 4 mW.

A 24-to-30 GHz Ultra-High-Linearity Down-Conversion Mixer for 5G Applications Using a New Linearization Method

The linearity of active mixers is usually determined by the input transistors, and many works have been proposed to improve it by modified input stages at the cost of a more complex structure or more power consumption. A new linearization method of active mixers is proposed in this paper; the input 1 dB compression point (IP1dB) and output 1 dB compression point (OP1dB) are greatly improved by exploiting the “reverse uplift” phenomenon. Compared with other linearization methods, the proposed one is simpler, more efficient, and sacrifices less conversion gain. Using this method, an ultra-high-linearity double-balanced down-conversion mixer with wide IF bandwidth is designed and fabricated in a 130 nm SiGe BiCMOS process. The proposed mixer includes a Gilbert-cell, a pair of phase-adjusting inductors, and a Marchand-balun-based output network. Under a 1.6 V supply voltage, the measurement results show that the mixer exhibits an excellent IP1dB of +7.2~+10.1 dBm, an average OP1dB of +5.4 dBm, which is the state-of-the-art linearity performance in mixers under a silicon-based process, whether active or passive. Moreover, a wide IF bandwidth of 8 GHz from 3 GHz to 11 GHz was achieved. The circuit consumes 19.8 mW and occupies 0.48 mm2, including all pads. The use of the "reverse uplift" allows us to implement high-linearity circuits more efficiently, which is helpful for the design of 5G high-speed communication transceivers.

Double-balanced mixer based on monolayer graphene field-effect transistors

Graphene field-effect transistors (GFET) have attracted much attention in the radio frequency (RF) and microwave fields because of its extremely high carrier mobility. In this paper, a GFET with a gate length of 5 μm is fabricated through the van der Walls (vdW) transfer process, and then the existing large-signal GFET model is described, and the model is implemented in Verilog-A for analysis in RF and microwave circuits. Next a double-balanced mixer based on four GFETs is designed and analyzed in advanced design system (ADS) tools. Finally, the simulation results show that with the input of 300 and 280 MHz, the IIP3 of the mixed signal is 24.5 dBm.

Differential Retrodirective Array With Integrated Circuits in Low-Cost 0.18 μm CMOS for Automatic Tracking

This communication presents a differential retrodirective array (RDA) for real-time tracking. The proposed differential RDA consists of three phase-conjugating chips and two circularly polarized antenna arrays. The phase-conjugating circuit chip which is in 0.18-um CMOS process, includes a differential low-noise amplifier, a double balanced mixer and a differential power amplifier. The specifically designed chip consumes 38.4 mW with a low voltage supply of 1.2 V. Experimental results of monostatic and bistatic cases show that, the RDA has a 3-dB beamwidth up to 77°. To the best knowledgement of the authors, the proposed RDA with circular polarization, which is promising for tracking free-moving targets, is the first differential RDA enabled by specifically designed low-cost CMOS chips.

Silicon Photonic-Based Integrated Microwave Photonic Reconfigurable Mixer, Phase Shifter, and Frequency Doubler

An integrated microwave photonic (IMWP) reconfigurable mixer, phase shifter, and frequency doubler based on the silicon photonics platform is proposed and theoretically investigated in this paper. The proposed structure consists of a novel dual-drive Mach–Zehnder modulator (DDMZM) placed in parallel with an electro-optic phase modulator (PM). The novel DDMZM is a bias-free modulator that has advantages over conventional MZMs, such as bias-free operation and tunable optical-to-carrier sideband ratio (OCSR). The proposed novel structure can be configured as an IMWP phase tunable mixer or IMWP double-balanced mixer by properly adjusting optical wavelength and choosing the proper radio frequency (RF) hybrid coupler. Besides, the proposed IMWP reconfigurable mixer has the ability to perform up-converting, down-converting, RF frequency doubling, and phase shifting. The proposed structure is theoretically analyzed and is verified by simulations.

A 16-Times Frequency Multiplier for 5G Synthesizer

This article presents 16-times frequency multiplier composing of two four-times frequency multipliers (quadrupler) in cascade connection. The proposed topology is new structure of tuned-frequency multiplier (TFM) for better harmonic rejection ratio (HRR) with wide frequency range and low power consumption. For accomplishing reliable output frequency band of 16–28 GHz, the whole band is divided into 64 subsidiary frequency bands by applying 6-bits digitally controlled capacitor-bank of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned tank. The proposed quadrupler is consisted of a harmonic generator (HG) and a cascode <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned buffer. The proposed HG topology is based on double balanced mixer (DBM). Unlike typical mixer bias, the bottom differential pair devices of the proposed HG are C-class biased to generate more desired the fourth order harmonic. In addition, to reduce power consumption and frequency conversion gain variations for the whole target frequency band, negative- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> differential pair is added in parallel to enhance the equivalent parasitic parallel resistance of the HG <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank while keep it from oscillation. Great efforts have been contributed to minimize process variation effects by simple but relatively accurate capacitance calibration. Furthermore, each <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tuned tank output amplitude is regulated by a loop to maintain same output swing for the best optimization of specifications such as power consumption and HRR. The proposed 16-times multiplier is fabricated on 65-nm complementary metal–oxide–semiconductor (CMOS) process and successfully tested. Chip die size 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding input/output (I/O) pads and average power consumption is only 6 mW for 16–28 GHz frequency band. Also, negligible phase noise degradation is achieved.