Dopingless TFET Research Articles

Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling junction. Similarly, use of dopingless silicon nanowire with CP has a genuine advantage in process engineering. Therefore, combination of both technology boosters (CP and NC) in the proposed device enable low thermal budget, process variation immunity, and excellent electrical characteristics in contrast with its counterpart dopingless (DL) TFET (DL-TFET). An optimized device accomplishes an impressive 10× improvement in on-current, 100× reduced leakage current, 3× more transconductance (gm), and on-off current ratio of ∼1011 as compared to DL-TFET.

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ∼ 0.56 mA/μm), ION/IOFF ratio ∼ 9.12 × 1013 and an average subthreshold swing (AV-SS ∼ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Analog performance investigation of dual electrode based doping-less tunnel FET

In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron's and hole's clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance $$(\hbox {g}_\mathrm{m})$$(gm), transconductance to drain current ratio $$(\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})$$(gm/ID), output-conductance (g$$_{d})$$d), output resistance $$(\hbox {r}_\mathrm{d})$$(rd), early voltage $$(\hbox {V}_\mathrm{EA})$$(VEA), intrinsic gain $$(\hbox {A}_\mathrm{V})$$(AV), total gate capacitance $$(\hbox {C}_\mathrm{gg})$$(Cgg) and unity gain frequency $$(\hbox {f}_\mathrm{T})$$(fT). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.

Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis

A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel. The performance of the proposed device is assessed using 2-D simulations. We establish the prospect of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with: 1) low OFF-state current and low sub-threshold swing (SS) and 2) an ON-state current similar to that of a comparable single grain boundary poly-silicon thin film transistor (TFT). Our results indicate that the proposed single grain boundary dopingless PNPN TFET could be an ideal substitute for the conventional TFTs making it appropriate for low power display applications as well as the driver circuits.

Dopingless PNPN tunnel FET with improved performance: Design and analysis

In this paper, we present a two-dimensional simulation study of a dopingless PNPN TFET with a hetero-gate dielectric. Using a dual-material-gate in a dopingless TFET, the energy band gap on the source side is modulated to create an N+ source pocket. Our technique obviates the need to use ion implantation for the formation of the N+ source pocket. The dopingless PNPN TFET with a hetero-gate dielectric is demonstrated to exhibit a superior performance in terms of ON-state current and subthreshold swing when compared to a conventional dopingless TFET. Our results may pave the way for realizing high performance dopingless TFETs using a low thermal budget required for low power and low cost applications.

A high performance gate engineered charge plasma based tunnel field effect transistor

In this paper, we propose a new gate engineered dopingless tunnel field effect transistor (GEDL-TFET). GEDL-TFET has double gate and uses metals of different work functions to realize source and drain regions in undoped silicon; a charge plasma concept. The novelty of the device is the use of dual material top gate and thus two gates appear at the top, main gate 1 and a tunneling gate (TG). The use of TG has enhanced the performance of the device significantly and it acts as a performance booster. The simulation study has shown that the $$\hbox {I}_{\mathrm{ON}}$$ION and $$\hbox {I}_{\mathrm{ON}}/\hbox {I}_{\mathrm{OFF}}$$ION/IOFF ratio in the proposed GEDL-TFET device have increased by $$\sim $$~53 times and $$\sim $$~68 times in comparison to a double gate doped TFET (D-TFET) and a double gate dopingless TFET (DL-TFET) devices respectively. Further, a significant improvement in average subthreshold slope of $$\sim $$~57% has been achieved in the proposed GEDL-TFET device in comparison to the other two devices. Besides, the cutoff frequency $$(f_{\mathrm{T}})$$(fT) of GEDL-TFET (90.77 GHZ) has increased by $$\sim $$~12 times in comparison to D-FET ($$\sim $$~7.77 GHZ) and DL-TFET ($$\sim $$~7.77 GHZ) devices respectively. The transient analyses have shown that a reduction of 47 and 44.11 % in switching ON-delay and 21.1 and 16.23 % in switching OFF delay is obtained in the GEDL-TFET device based inverting amplifier in comparison to DL-TFET and D-TFET based inverters amplifiers respectively.

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.