Substrate Doping Concentration Research Articles

Metal-InP(110) interface properties: Temperature, dopant-concentration, and cluster-deposition dependencies.

Synchrotron-radiation photoemission has been used to investigate the movement of the surface Fermi level, ${\mathit{E}}_{\mathit{F}}$, in the gap as a function of temperature, bulk dopant concentration, and the technique of interface formation for Ag/InP(110) and Ti/InP(110). Studies involving atom deposition at 300 and 60 K reveal temperature-independent substrate disruption with substrate retreat that is estimated to be \ensuremath{\sim}4.4 monolayers (ML) for Ti and \ensuremath{\sim}1 ML for Ag deposition. Atom distributions differ, however, because In atoms released by substrate disruption are kinetically trapped near the interface at 60 K but they are distributed in and atop the metal overlayer at 300 K. Moreover, Ag deposition at 60 K produces uniform overlayers because of restricted surface mobility whereas Ag clustering occurs for atom deposition at 300 K. Despite these significant differences in interface chemistry and morphology, both overlayers induce very different amounts of band bending at 60 K than at 300 K for n-type InP(110) doped at 4\ifmmode\times\else\texttimes\fi{}${10}^{17}$ ${\mathrm{cm}}^{\mathrm{\ensuremath{-}}3}$. This temperature-dependent difference in band bending is significantly smaller for n- and p-type InP(110) doped at 2.5\ifmmode\times\else\texttimes\fi{}${10}^{18}$ ${\mathrm{cm}}^{\mathrm{\ensuremath{-}}3}$. At higher coverage above the metallization threshold, the Schottky-barrier height is largely independent of substrate dopant concentration or measurement temperature but exhibits metal-specific values for Ag and Ti overlayers. The relationship between ${\mathit{E}}_{\mathit{F}}$ movement and the details of interfacial bonding and morphology has been further examined by depositing preformed Ag clusters (rather than atoms) on pristine InP(110) surfaces. For cluster deposition, there was no noticeable substrate disruption and the Fermi-level position was not dependent on the size or number of clusters. This indicates that changes in surface relaxation under and around the clusters introduce states that determine band bending.

Gate oxide thinning as related to doping effects

AbstractGate oxide thinning induced by selective oxidation process has been studied. Tests on samples having both high and low boron doping concentration after wet oxidation of 9 and 50 h, have shown that gate thinning phenomenon is related to substrate doping concentration for p‐type silicon. The chemical resistivity of the nitride or oxynitride layer, which is assumed to be responsible for the gate thinning, has been tested and it also results to be related to the substrate boron concentration. A possible interpretation of the occurrence of the doping effect is given.

On the performance limit for Si MOSFET's: experimental study

Short-channel MOSFETs fabricated by direct-write electron-beam lithography have been examined with regard to parameters such as channel length, oxide thickness, and substrate doping concentration. A simple relationship between channel length and transconductance in the saturated region has been derived from the experimental results, and the performance of MOSFETs with zero channel lengths has been evaluated as a function of oxide thickness. The ultimate performance of MOSFETs with both zero channel length and zero oxide thickness has been estimated to be about 3000 mS/mm. This limitation is attributed to the saturation velocity and the finite inversion layer thickness. The electron saturation velocity in the inversion layer has been confirmed experimentally to be 1.0*10/sup 7/ cm/s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Growth of Anodic Al2 O 3 / Native Oxide Double Layers on InP

Models for the controlling mechanisms of anodic growth of native oxides under an anodized Al film on are presented. These models for constant current anodization use charge flow over and through the interfacial energy barrier to explain the observed oxide growth behavior. They account for changes in the interfacial barrier height due to variations in substrate doping type and concentration and for changes in illumination conditions. For anodization to proceed on low‐doped n‐type , holes must be generated by either impact ionization or illumination. With low‐doped p‐type, the interfacial barrier must be reduced by applying an overvoltage or creating energetic carriers with illumination. Increasing the doping concentration reduces the barrier to current flow; thus, neither illumination or increased voltage is required.

A simple technique for measuring the interface-state density of the Schottky barrier diodes using the current-voltage characteristics

A simple technique for measuring the interface-state density of a Schottky barrier diode fabricated on the moderately doped semiconductor is presented. It requires the I-V characteristics and substrate doping concentration as inputs which can be easily measured by existing techniques. Checked by the Schottky capacitance spectroscopy method, the proposed technique is proved to be highly accurate for various metal-Si and metal silicide-Si Schottky barrier diodes.

Al‐doped Ni–Cr for temperature coefficient of resistance control in hybrid thin‐film resistors

The temperature coefficient of resistance (TCR) was tailored by doping standard 60/40 nickel–chromium resistor film to reduce the TCR from ∼100 ppm/°C to ∼0 ppm/°C. For constant sheet resistance films, TCR was a function of both substrate surface roughness and dopant concentration. TCR may be kept near zero for a wide variety of hybrid substrate materials with varied surface finishes by changing dopant concentration in the sputtering target. By controlling alloy composition to 0.1 wt. %, using powder metallurgy techniques, TCR was controlled to ±5 ppm/°C for a constant sheet resistance and invariant substrate surface finish. Because rough substrates required thicker films to obtain the same sheet resistance, the factors which controlled TCR were slightly modified. The effect was an increase in TCR for the same resistance value. Doped resistors on aluminum oxide were slightly less stable in the high temperature storage test than undoped resistors. However, because their TCR was so much lower, the change in resistance during operation of a real circuit was less than one‐fourth the change in undoped resistors used on the same circuit.

Zn diffusion in InP: Effect of substrate dopant concentration

We have performed open-tube diffusion of Zn into n-type InP over the temperature range 525–675 °C. For heavily doped InP, the observed diffusion profiles are consistent with an interstitial-substitutional model where the interstitial Zn is doubly ionized. However, for undoped InP the profiles have a significantly different shape and the diffusion is deeper. Assumption of neutral interstitial Zn is able to account for these two changes. A tentative model is proposed to explain the dependence of the interstitial Zn ionization state on the starting substrate dopant concentration.

MOSFET drain breakdown voltage

The grounded-gate or gate-assisted drain breakdown voltage of n-channel MOSFET's has been characterized for wide ranges of oxide thickness and substrate doping concentration. Two distinct regimes, one being channel-doping limited and the other being oxide-thickness limited, have been identified. We propose that these two regimes reflect two possible locations of breakdown-at the n+-p junction and in the deep-depletion layer in the n+ drain. They can be separated by their different breakdown voltage dependences on V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> and require different approaches to process improvement.

Threshold voltage of small-geometry Si MOSFETs

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.

Breakdown voltages of ion-implanted junctions

In this paper an analytic analysis of the breakdown voltage of an ion-implanted junction is presented. A joined half-Gaussian distribution of the implanted ions is used, since it gives better description of the impurity profiles. The results are based on a closed-form solution of Poisson’s equation in the depletion region. Fulop’s average ionization coefficient is used to determine the values for the avalanche breakdown voltage as a function of implantation energy, implant dose, and substrate dopant concentration. The maximum electric field at junction breakdown is also calculated and the results are presented. Finally, the applicability and restrictions of the analysis are discussed.

Selective epitaxial growth for the fabrication of CMOS integrated circuits

A process is described for the fabrication of CMOS integrated circuits which combines the epitaxial lateral overgrowth (ELO) technique with the concept of selective epitaxy. The resulting epitaxial material is shown to have a low defect density. Transistors fabricated in the selective epitaxy are shown to have characteristics which are a function of the epitaxial deposition conditions, the substrate orientation and dopant concentration, and the epitaxial layer thickness. Minimum device leakage currents were 250 pA/µm of channel width for n-channel devices fabricated in a p-well and 1.0 pA/µm for devices fabricated on p-substrates. The higher leakage currents for devices fabricated in a well are believed to be a result of the narrow vertical spacing (0.3-0.5 µm) between the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source-drain regions and the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate.

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (V D ), and an inverse dependence on oxide capacitance (e ox /t ox ). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (t ox , V D , L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.

A study of the trench surface inversion problem in the trench CMOS technology

This paper presents the results obtained in the study of the trench surface inversion problem for the CMOS technology using trench isolation. Special emphasis is put on the n-well CMOS technology where the inversion problem is most severe. Potential distribution along the trench surface is simulated using the SUPREM and GEMINI programs for different bias conditions, as well as for different impurity doping profiles and fixed charge densities (Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</inf> ). The results showed that Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</inf> along the trench surface has to be maintained at 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> if the substrate doping concentration remains at 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . Higher substrate doping, lower n-well bias, and more negative substrate bias will help prevent trench surface inversion. p-well CMOS is more suitable for trench isolation due to the higher doping concentration inside the p-well. Experimental data showed that trench isolation gives no improvement in latch-up susceptibility when the trench surface is inverted.

A method for routine characterisation of the hole concentration in p-type cadmium mercury telluride

Recently there has been growth of interest in the fabrication of photodiodes in CMT, for use in electronically scanned hybrid focal plane arrays. Most devices are currently fabricated using a p-type wafer with an n-type surface layer introduced either by ion implantation or diffusion. In both types of junction the &,A product is dependent on the net doping concentration of the p-type substrate. In ion-implanted junctions for example the performance can be limited even at zero bias by the junction tunnelling current if the substrate doping is too high. It has been determined that a carrier concentration of 1 x 1Ol6 cme3 or less is required to produce implanted detectors with high zero bias resistance-junction area, R,,A, products. (l) Consequently an accurate, and rapid, method of determining the carrier concentration of p-type CMT is required. A common method of determining the net carrier concentrations in routine characterisation of semiconductors is to measure the Hall coefficient, RH, at a single temperature in the exhaustion range of the extrinsic conduction region. This method, using a spot measurement at 77K, has been found to be satisfactory for n-type CMT in which carrier freeze-out is not observed. However, p-type CMT is much more difficult to characterise by Hall effect measurements because of the high electron-to-hole mobility ratio, b, (500 at 80K) and a relatively high intrinsic carrier density in this narrow gap semiconductor. As a result the mixed conduction region in lightly doped p-type samples extends below 80K and may overlap the freeze-out region so that no exhaustion region is observed. Determination of the net doping concentrations in p-type material has therefore required the interpretation of Hall data obtained over a range of temperatures extending down to about 20K. The interpretation may be further complicated since oxidation of the surface of the samples can lead to an n-type skin which shunts the sample at low temperatures and in extreme cases can cause a p-type sample to appear in n-type. To overcome these difficulties the possibility of using a measurement of bulk conductivity to characterise the hole concentration has been investigated. The two band expressions for conductivity, 0, and low field Hall coefficient, RH are:

Sprayed SnO 2 films: Growth mechanism and film structure characterization

Transparent conductive tin oxide layers doped with antimony were produced by an inexpensive spraying method in the temperature range of 573–923 K. The substrates were soda glass and polished 〈111〉 silicon wafers. The growth rate and crystalline structure were studied as functions of the deposition parameters. The growth rate was independent of the substrate type, dopant concentration, and time deposition. As a function of temperature, the growth rate showed an activation energy of 0.48 eV at the lowest deposition temperatures, becoming constant at the highest deposition temperatures, for a constant reactant flux. The growth rate was a rising function of the flux rate of reactants for low flux rates, becoming flux independent at highest flux rates, at constant substrate temperatures. The crystalline structure of the films was a function of the substrate temperature only, resulting in structures that were amorphous below 623 K and polycrystalline above. The films showed preferential growth directions as a function of temperature but they developed no preferential growth direction in the highest temperature range. The crystalline size showed a tendency to increase as the deposition temperature was increased. The grain size was in the range of a few hundreds of ångströms.

Analysis of C- V data in the accumulation regime of MIS structures

Hynecek's method for deriving flat band from C- V data of MIS structures in the accumulation regime is modified to provide a precise determination of the insulator capacitance. The effect of interface states on flat band determination is discussed and it is shown that an upper limit on the surface state density can be obtained from high frequency measurements in the accumulation regime without requiring the substrate dopant concentration.

P-MOSFET parameters at cryogenic temperatures

p-channel MOSFET parameters measured at 300 K, 77 K, and 4.2 K are discussed; these include I-V characteristic curves, channel conductance, transconductance, threshold voltage, field effect mobility, and forward and reverse p+n junction characteristics. Some qualitative explanations of the dependence of the data on temperature and substrate doping concentration are given. Interesting LHe phenomena are highlighted and discussed in terms of accepted solid state models.

Scheduling an IC tester for maximum throughput

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V BD , however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V BD , however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

Impurity Atom Transfer during Epitaxial Deposition of Silicon

When epitaxial silicon is deposited on highly doped substrates, impurity atoms transfer from the substrate to the growing epitaxial film. This transfer, usually referred to as autodoping, may establish a lower limit on the dopant concentration in the epitaxial film and may prevent the formation of an abrupt doping profile. We have studied the transfer of arsenic during the deposition of epitaxial silicon by the pyrolysis of silane at a temperature of 1050° C. The amount of autodoping is determined from the flat portion of the doping profile and has been studied as a function of the substrate dopant concentration. The data are interpreted in terms of solid‐state diffusion theory by assuming that during deposition the arsenic diffuses to the back of the substrate, evaporates from the back surface, transfers in the gas phase to the front surface, and then is incorporated into the film. Calculations indicate that 0.9% of the arsenic that evaporates from the back surface is deposited into the epitaxial film. Our results show that autodoping is linearly dependent on the substrate doping concentration and becomes significant when the arsenic concentration is greater than . The autodoping can be reduced by a factor of about five by masking the back of the substrate with silicon oxide or by heating the substrate at a high temperature for a few minutes to allow the arsenic near the back surface to evaporate prior to deposition.