Drain voltage limitations of MOS transistors

Abstract

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V BD , however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V BD , however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.