Doped Polycrystalline Si Research Articles

Realignment of As doped polycrystalline Si films by double step annealing

The realignment by rapid thermal annealing of polycrystalline silicon layers deposited onto 〈100〉 Si substrates can occur either through the planar movement of the interface towards the surface or through the lateral growth of columnar epitaxial islands. An anneal at 1075 °C for 15 s, followed by As implantation, is shown to cause planar growth even at subsequent anneal temperatures as low as 900 °C. In contrast, the direct annealing of As implanted samples induces columnar realignment. Further, the As redistribution throughout the polycrystalline layers and its diffusion in the crystalline substrate is considerably reduced in the case of the double step annealing. The different regrowth modes are related to the morphology of the interfacial oxide layer and to the microcrystalline structure of the polycrystalline layers during the initial stages of the realignment process.

Selective epitaxial growth with oxide-polycrystalline silicon-oxide masks by rapid thermal processing chemical vapor deposition

We have used rapid thermal processing chemical vapor deposition for Si selective epitaxial growth using a mask consisting of a sandwich structure of SiO2 on doped polycrystalline Si on SiO2. Lateral polycrystalline Si growth from the sidewalls of the polycrystalline Si layer was also observed and resulted in polycrystalline ‘‘bumps’’ along the mask sidewalls. Otherwise, the epitaxial Si layer was defect-free.

High‐performance BIMOS using self‐aligning polysilicon electrode

AbstractTo increase the speed of Hi‐BiCMOS, the process of forming an electrode which simultaneously reduces both parasitic capacitance and parasitic resistance in MOSFET's and bipolar transistors was investigated.Since the etching rate of highly doped polycrystalline silicon is higher than undoped polycrystalline silicon, arsenic‐doped polycrystalline silicon on the gate and emitter electrodes can be etched selectively. Self‐aligned polycrystalline silicon electrode technology (SPEL) using this phenomena was proposed.When the As concentration in polycrystalline Si is higher than 4 × 1020 cm−3, the doped polycrystalline Si is etched 10 times faster than undoped polycrystalline Si if plasma etching based on chlorine radicals is carried out.Using this process, the drain capacitance of the MOSFET was reduced one‐half to one‐third that of conventional devices. In bipolar transistors, collector resistance was reduced by a factor of 2 and the external base resistance was reduced by a factor of 3. As a result of simulating the performance of the device formed by the SPEL process, the gate delay time in a dual input NAND BiCMOS was 0.19 ns under no‐load condition while the gate delay time of the conventional device was 0.26 ns; that is, the speed of the SPEL device is 25 percent faster than that of the conventional device.

Thin-film transistors from very low temperature polycrystalline Si on glass substrates

Polycrystalline Si films were deposited onto glass substrates by evaporation technique. The Hall-mobility of undoped films was investigated for process substrate temperatures from 300 to 650°C. The Hall-mobility was found to be up to about 10 cm 2/Vs for 500°C. Sb-doped n-type films exhibited a conductivity up to 10 (Ω cm) −1 deposited at about 500°C. Thin film transistors were fabricated from undoped and doped polycrystalline Si used for the channel and the source/drain contacts. The TFT mobilities were found to be 10 cm 2/Vs and 2 cm 2/Vs for a highest process temperature of 550°C and 480°C respectively. The new feature of the TFT process is that these data were obtained without using ion implantation technique. For the first time a poly-Si TFT was fabricated on soda-lime glass at a very low temperature of 480°C.

Determination of grain-boundary potential barriers distribution in p-type polycrystalline Si

Metal-oxide-semiconductor structures employing lightly boron doped polycrystalline Si electrode are studied. The frequency dispersion of their admittance is explained by the existence of a broad distribution of intergrain potential barriers. A simple one-dimensional model is presented which yields the form of the potential barrier distribution. The observed results for the temperature and doping concentration dependence of the distribution are described and shown to be consistent with the resistivity activation energies.

The Diffusion of Phosphorus and Indium into Gallium Arsenide from Polycrystalline-Silicon

ABSTRACTArsenic or phosphorus doped polycrystalline-Si (poly-Si) acts as a diffusion source when deposited on GaAs. Non-Fickian Si diffusion into GaAs has been observed following heat treatments above 700°C. In this paper, the diffusion of In and P from poly-Si at temperatures between 800 and 1020°C is presented. These impurities, introduced into the poly-Si by in-situ plasma deposition, implantation or vapor annealing, diffuse rapidly into the GaAs. Results from particle induced x-ray analysis, transmission electron microscopy, Rutherford backseat tering and secondary ion mass spectroscopy indicate 80% substitutional In and P at interface concentrations of approximately 10 and 25 at%, respectively.

Analysis of Multicomponent LPCVD Processes: Deposition of Pure and In Situ Doped Poly‐Si

A general model has been developed for multicomponent‐multireaction systems in the hot‐wall multiple‐wafers‐in‐tube LPCVD reactor. The modeling equations describe the coupled convective and diffusive mass fluxes in the annular reactor flow region as well as those between each pair of wafers. Complex reaction mechanisms involving both gas‐phase and surface reactions can be included in the model formulation. Multicomponent transport effects in the deposition of pure and doped polycrystalline Si are analyzed. The model predicts experimentally observed growth rates for pure polycrystalline Si quite well. However, because of insufficient data, a comparison of model predictions and experimental growth rates has not been feasible for in situ doped Si. The model is also used to predict the performance of a new continuous moving boat LPCVD reactor offering excellent film uniformity and process automation.

Resistivity reduction in heavily doped polycrystalline silicon using cw-laser and pulsed-laser annealing

The resistivity reduction in heavily doped polycrystalline Si by laser annealing and its increase during subsequent heat processing have been studied. Both cw and pulsed lasers have been used for the experiments and the results are compared. In both cases laser annealing reduces the Si resistivity by a factor of 2–3 compared to the furnace annealing. A limited resistivity increase is observed in all laser-annealed Si samples during subsequent thermal annealing, with the final values for resistivity being lowest for cw-laser-annealed Si. The subsequent annealing behavior observed for cw- and pulsed-laser-annealed Si is interpreted in terms of the different grain structures found in these films. It is demonstrated by transmission electron microscope studies that the resistivity instability is caused by the precipitation of dopants in the form of rod shaped structures localized at the grain boundaries as well as within the crystallites.

Optical determination of mobility and carrier concentration in heavily doped polycrystalline silicon

Optical absorption of phosphorus-doped polycrystalline Si films observed at photon energies below the energy gap has been interpreted in terms of free-carrier absorption, which obeys the Drude theory. As a result, we can simultaneously determine conductivity, electron mobility, and carrier concentration of heavily doped polycrystalline Si films from their optical transmission spectra alone. The new technique offers a contactless measurement of electrical properties for heavily doped polycrystalline Si thin films.

Anomalous Resistivity Change in B Doped Polycrystalline Si Caused by BN Formation under N2 Heat-Treatment

B doped Si films were obtained by thermal decomposition of SiH4-BCl3-H2 gas mixture at 550°C onto thermally grown SiO2 and were heat-treated in N2 or Ar at 1100°C. The B doped polycrystalline Si exhibits an anomalous increase in resistivity for N2 heat-treatment. IMA, AES, EM and IR measurements reveal that the resistivity increase is due to decrease in B concentration in polycrystalline Si, which is caused by BN formation near the polycrystalline Si surface. The decrease rate of B concentration in polycrystalline Si and BN formation rate were measured and it is concluded that BN formation rate is determined by B and N reaction velocity.

Boron and phosphorous diffusion through an SiO 2 layer from a doped polycrystalline Si source under various drive-in ambients : K. Shimakura, T. Suzuki and Y. Yadoiwa. Solid State Electronics18, 991 (1975)

Boron and phosphorous diffusion through an SiO 2 layer from a doped polycrystalline Si source under various drive-in ambients : K. Shimakura, T. Suzuki and Y. Yadoiwa. Solid State Electronics18, 991 (1975)

Boron and phosphorus diffusion through an SiO2 layer from a doped polycrystalline Si source under various drive-in ambients

The diffusion of boron and phosphorus into thermally grown SiO2 from a doped polycrystalline Si source has been found to be dependent on drive-in ambients and to be especially fast in an H2 ambient. Diffusion coefficients have been calculated by the two boundary diffusion model. It was found that the diffusion coefficient of boron in SiO2 is about two orders of magnitude larger than that of phosphorus. This fact is very important for Si gate processes. For P-channel Si gate transistors, boron diffused in the gate SiO2 film from the doped polycrystalline Si gate electrode causes new types of instabilities in transistor characteristics.

Technology for monolithic high-power integrated circuits using polycrystalline Si for collector and isolation walls

The fabrication technology for a high-power monolithic IC improved the breakdown characteristics and the output current capability. The maximum output power increased to 50 W and the supplied voltage of 110 V was realized. Highly doped polycrystalline Si was used as the collector walls and the isolation walls of transistors. Electrical and physical properties of the polycrystalline structure used in the power IC and the fabrication technology are also described.

Performance of refractory metal multilevel interconnection system

High-temperature multilevel interconnection systems are discussed from a materials fabrication, yield, and circuit performance point of view. Refractory metal interconnections are compared to diffused Si planar runs and heavily doped polycrystalline Si films. Circuit configurations and their relative importance for these material-circuit performance considerations are considered. All of the high-temperature refractory systems will have higher yield and better passivation properties than many low-temperature systems. Metallic interconnections are always best from a circuit performance point of view. The relative difference between the high-temperature systems considered depends on circuit configuration. In particular, high-temperature refractory metal (Mo, W) interconnections which are a natural by-product of the self-registered refractory metal gate MOS technology (RMOS) are superior for memory circuits where long address lines are used.