Doped Contact Layers Research Articles

Noise performance of submicrometer AlInAs-GaInAs HEMTs

Record DC and RF performance of AlInAs-GaInAs lattice matched to InP HEMTs (high-electron-mobility transistors) with nominally 0.2- and 0.1- mu m gate lengths have been achieved. The devices were fabricated on material grown by MBE (molecular-beam epitaxy) on Fe-doped InP substrates. The epitaxial layers consisted of an undoped AlInAs spacer, a highly doped AlInAs donor layer, an undoped Schottky-enhancing AlInAs layer, and, finally, a highly doped GaInAs layer contact layer. 50- mu m-wide devices with 0.2- and 0.1- mu m-long T-gates were fabricated. The 0.2- mu m gate-length devices were tested at V-band. The single-stage amplifier (waveguide to waveguide with no correction) exhibited a minimum noise figure F/sub min/ of 1.8 dB with an associated gain 7.5 dB at 63.0 GHz. This translates to an amplifier noise measure of 2.10 dB. The corresponding device performance was a minimum noise figure of 1.4 dB with an associated gain of 8.5 dB. This corresponds to a device noise measure of 1.6 dB.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Band offsets, Fermi levels and impurity bands in doped contact layers

A Hartree-Fock model for impurity bands is used to obtain a simple, approximate correction to the free electron model which is almost universally used in treatments of doped contact layers in quantum well, heterojunction and modulation doped devices. The operation of such devices depends critically on band offsets and Fermi levels. The model incorporates exchange interactions as well as screening and it is analytically solvable. The results are cast in such a form as to facilitate use in modeling the effect of contact layers in the aforesaid devices. Numerical results for shallow dopant band offsets in GaAs are found to be about 10%–25% of the Fermi energy.

Models for ohmic contacts on graded crystalline or amorphous heterojunctions

A one-dimensional model for sandwich-type graded heterojunctions is presented to explain the formation of contacts that cannot be based on highly doped contact layers, such as indium contacts to GaAs and GaSb. In this model a hyperbolic dependence on distance for the permittivity and a constant space charge density owing to filled interferance states is assumed. Algebraic solutions have been obtained for the barrier height and capacitance of a wide variety of heterojunctions. The conditions for zero barrier height, i.e. ohmic contacts, are discussed. The graded heterojunction model is also applied to heterojunctions formed by an amorphous and a crystalline semiconductor to explain the formation of ohmic contacts in cases where neither doping nor crystalline heterojunction effects can be assumed, such as Au, Ag, InAu, InAg and AuNi metal contacts to GaAs, GaSb or GaP.

Infrared transmissivity of heavily doped contact layers on extrinsic silicon IR-detectors

The infrared transmissivity of heavily dopedp-type contact layers on silicon was studied in the 3–5 μm and 8–14 μm wavelength range in order to optimise the layer thickness and doping concentration for antireflection coating. The transmissivity of surface layers and buried layers was computed taking into account the free carrier optical dispersion by the Drude theory and corrections due to intervalence band transitions as well as multiple reflections and interferences in the layer. The computations are in quantitative agreement with measurements on contact layers formed by multiple boron implantation. It was found that the free carrier absorption loss completely cancels the gain due to the antireflection effect for a surface layer. Transmissivities of around 73% may be obtained by a buried heavily doped layer.

Physical and materials limitations on burnout voltage of GaAs power MESFET's

This paper presents a study of factors limiting the burnout voltage of GaAs power MESFET's. A new device geometry had been investigated. Novel techniques using electron-beam induced current (EBIC) in the drain loop in a scanning electron microscope (SEM) and the shift in carbon Auger line in a scanning Auger microscope (SAM) have been applied to study the bulk electric field distribution and the surface voltage distribution. These techniques have been used to identify the regions of high electric field that lead to device burnout. The highest burnout voltages were observed at 8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> -cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> doping with at least 60-V burnout at full channel current and 85 V near pinchoff conditions. This is a new state of the art. An optimum undoped buffer-layer thickness is observed to be compatible with high burnout voltage and low leakage current. Finally, under optimized conditions of doping and geometry, no improvement is observed in the burnout voltage with the use of a higher doped contact layer.

Optimum i-layer width of p-i-n diodes for frequency multipliers

p-i-n diodes give their best possible performance as charge-storage diodes in frequency multipliers. The paper deals with the optimum design of the diode parameters to minimise the power loss in the diode. D.C. losses due to recombination of charge carriers and ohmic losses due to the ramp voltage during the turn-off transient are shown to be the most important loss components. Because recombination losses dominate for a small and turn-off losses for a large i-layer width, this design parameter can be optimised. Based upon closed-form solutions for the diode current and the various loss components, the optimum i-layer width is determined and related to the doping concentrations in the highly doped contact layers and to the input frequency of the multiplier.

Optimum i-layer width of p-i-n diodes for frequency multipliers

p-i-n diodes give their best possible performance as charge-storage diodes in frequency multipliers. The paper deals with the optimum design of the diode parameters to minimise the power loss in the diode. D.C. losses due to recombination of charge carriers and ohmic losses due to the ramp voltage during the turn-off transient are shown to be the most important loss components. Because recombination losses dominate for a small and turn-off losses for a large i-layer width, this design parameter can be optimised. Based upon closed-form solutions for the diode current and the various loss components, the optimum i-layer width is determined and related to the doping concentrations in the highly doped contact layers and to the input frequency of the multiplier.