Dopant-segregated Schottky Barrier Research Articles

Study of variability induced by random dopant fluctuation in Fe DS-SBTFET

This paper explores the affectability of random dopant fluctuation (RDF) on the performance of Ferroelectric Dopant Segregated Schottky Barrier (Fe DS-SB) TFET by utilizing 3-D TCAD simulation. The simulation technique involves the device bifurcation into rectangular coordinates where the doping charges are placed randomly as individual and discrete dopants. Threshold voltage varies significantly due to variation in source-channel dopant concentration. The dependency of threshold voltage standard deviation on various source doping concentration has been studied. Doping variability within the channel and drain regions mainly leads to alteration in ON state current. Moreover, the impact of temperature (300 K–500 K) on switching characteristics of the proposed device has been investigated.

Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current

In this paper, to solve the problem of higher ambipolar leakage current (Iambipolar) of Dielectric Engineered (DE) Dopant Segregated (DG) Schottky Barrier (SB) MOSFET (DE DS SBMOS), we have incorporated dual metal gate (DMG) in place of single metal gate for the DE DS SBMOS. The proposed device is named as DMG DE DS SBMOS. In a proposed device, the gate is consisting of dual metal having different work functions. Therefore, the gate is divided in two parts named as auxiliary gate (AG) and tunneling gate (TG). AG and TG employed near the source and drain (S/D) ends, respectively. AG is mainly used to control the on-state performance and TG for the off-state performance by modulating the SB height and width at S/D end, respectively. Simulation results show that Iambipolar of the device has been successfully suppressed by choosing appropriate work functions for AG and TG without affecting the on-state current (Ion) of the device. The proposed device combines the advantage of dual metal gate and dielectric engineering to achieve improvement in the overall performance of the device. The proposed device exhibits high Ion, low Iambipolar and low subthreshold swing (SS). The simulations study verifies the use of the proposed device for low power applications.

Deep insight into material-dependent DC performance of Fe DS-SBTFET and its noise analysis in the presence of interface traps

This paper reports the DC performance of Ferroelectric Dopant Segregated Schottky Barrier TFET (Fe DS-SBTFET) for different types of materials in the Dopant Segregated (DS) layer and its noise analysis considering the presence of Gaussian and uniform interface traps with the device being subjected to variation in ferroelectric thickness. Silicon doped HfO2 ferroelectric layer increases the tunneling junction electric field. Maximum ION/IOFF ratio of 1.2 × 109 and 14 mV/dec Subthreshold Swing (SS) have been achieved by using ferroelectric layer of thickness 6 nm. Different electrical parameters such as SS and ION/IOFF ratio have been explored for various trap concentrations. ON state current deteriorates with the increase in trap concentration. The dominancy of different noise components has been analysed with respect to frequency. Both flicker noise and generation-recombination noise contribute to the net noise at low frequency range. Flicker noise dominates at mid frequency and the major contribution at high frequency is of diffusion noise.

Effect of Temperature on Reliability Issues of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET)

This paper addresses reliability issues associated with temperature of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET). The simulated results are compared with Dopant Segregated Schottky Barrier TFET (DS-SBTFET). This is achieved by varying the operating temperature from 300 to 500 K. DC parameters such as ION/IOFF ratio, drain current characteristics and subthreshold swing (SS) for a range of temperature have been highlighted. Moreover, the influence of temperature on various RF figure of merits such as gate capacitance (CGG), intrinsic delay, cutoff frequency (fT) etc. have been investigated. The device linearity has been analyzed by considering the effect of temperature variation on linearity parameters like gm2, gm3, 1-dB compression point, VIP2, VIP3 and IIP3. The device characteristics get upgraded by the increase in cut-off frequency and reduction in intrinsic delay at elevated temperature.

Optimisation of electrical parameters in Fe DS-SBTFET and its application as a digital inverter

ABSTRACTIn this paper, the design geometry of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET) has been proposed. Various electrical properties such as ION/IOFF ratio and subthreshold swing (SS) of the proposed design have been premeditated and compared with different asymmetric structures. The impact of various types and thickness of buffer on the ferroelectric properties have been analysed. The device has been optimised for various doping concentrations and lengths of the dopant segregated layer (DSL). The digital applications of the proposed device in terms of complementary TFET digital inverter circuit have been studied. The transient characteristics and the delay parameters by considering various ferroelectric thicknesses have been analysed. Moreover, the transfer characteristics and electric field have been explored in the presence and absence of ferroelectric layer to obtain a better insight into the ferroelectric properties of the proposed structure. The electric field at the tunnelling junction is enhanced by the presence of ferroelectric layer which improves the ON current. The structure with ferroelectric thickness of 6 nm provides the best ION/IOFF ratio of 1.2 × 109 and SS of 14 mV/dec.

Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain

In this paper, to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS), we have reported a novel dielectric engineered (DE) dopant segregated (DS) SBMOS structure using gate dielectric engineering. In a proposed device, we employ two different gate dielectric materials. The high-k gate dielectric is used at the source side and low-k gate dielectric at the drain side. Beneath the high-k gate dielectric, electron accumulation increases due to large gate dielectric capacitance density. As a result, reduction in depletion of source side dopant segregation layer further decreases the SB tunneling width for the electron injection. Consequently, improvement in ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is obtained. In addition, the low-k gate dielectric and drain side dopant segregation layer increases the effective SB height and tunneling width for the hole injection. Thus, the OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) is suppressed. The optimization of proposed device has been performed by modulating the length of high-k and the low-k gate dielectric. In addition, we have compared the performance of the proposed device in terms of ON to OFF current ratio $({I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}})$ , subthreshold swing (SS), transconductance $({g}_{ {m}})$ , transconductance generation factor $({g}_{ {m}}/{I}_{ {D}})$ , cut-off frequency $({f}_{ {T}})$ , and gain-bandwidth product $({f}_{ {A}})$ to the SBMOS, DS SBMOS, and DS SBMOS with the full high-k gate dielectric. Moreover, we have proposed the possible process flow for the DE DS SBMOS fabrication.

Metallic Schottky barrier source/drain nanowire transistors using low-temperature microwave annealed nickel, ytterbium, and titanium silicidation

This work presents the formation of intrinsic and dopant-segregated Schottky barrier nanowire transistors using microwave-annealed silicidation. To gain a sound understanding of applying the microwave annealing on fabricating metallic source/drain nanowire devices, three metals, nickel, ytterbium, and titanium, were utilized to form the Schottky barrier source/drain. Effects of microwave annealing on silicidation as well as segregation were intensively examined by comparing with those using rapid-thermal annealing. The drain current of ytterbium-based examples depend mildly on the applied microwave power from 200–400%, whereas the higher 300% or 400% power is most appropriate to optimize nickel-based nanowire transistors. The maximum 500% power is required on forming titanium silicidation for intrinsic or dopant-segregated nanowire devices. Relatively, temperature of 600℃ is required to form the nanowire source/drain with nickel or ytterbium, and temperature of 900℃ is needed for titanium-based devices. Experimental results show that the microwave annealing offers low-temperature processing against the rapid-thermal method to ensure favorable device characteristics, serving as a promising approach for 3D integration of CMOS technologies.

DS Schottky barrier cylindrical GAA MOSFET: nanosensor for biochips

This paper presents an extensive mathematical study of a proposed nanogap-embedded dopant-segregated (DS) Schottky barrier (SB) cylindrical gate all-around (CGAA) metal-oxide-semiconductor field-effect transistor (MOSFET) of negatively/positively charged and neutral species observed by numerical simulation using an Atlas three-dimensional device simulator for electrical and label-free detection of bio/chemical (DNA, pH) and neutral species (protein) respectively as a nanosensor in the biomedical field at high sensitivity for direct electronic readout. This is the first time that the use of a nanogap-embedded DS-SB-CGAA MOSFET as a bio/chemical sensor has been reported. The threshold voltage (V th) shift and change in current are considered as sensing metrics to detect biological or chemical species when they are immobilized in the carvel-built region. The shift in on current (I on) of the nanogap-embedded DS-SB-CGAA MOSFET is also taken as a sensing metric, and better performance is observed compared to a conventional SB-CGAA MOSFET sensor. It is advantageous in terms of its low power/energy consumption as well as from the point of view of integration with the forthcoming silicon-based lab-on-chip systems due to the compatibility with the complementary metal-oxide semiconductor process.

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

This paper presents a detailed Monte Carlo study of the optimization of the dopant segregation (DS) layer in n-type Schottky barrier (SB)-MOSFET. It is shown that with a careful control of the DS layer parameters, dopant concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dop</sub> ), and length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dop</sub> ), the performance of the devices is significantly enhanced. The presence of the DS layer induces crucial effects in the injection processes at the Schottky contacts. The benefits of increasing the length and the doping level of the DS layer are studied from the microscopic point of view (transit times, average number of scatterings). The effect of varying these parameters is also analyzed through the nonquasi-static parameters of the small signal equivalent circuit, which can be useful for designers to improve the reliability of the SB-MOSFET technology.

Dopant segregated Schottky barrier nanowire transistors using low-temperature microwave annealed ytterbium silicide

Thermal budget is one of the major concerns to fabricate three-dimensional (3D) transistors using practical CMOS technologies. In this work, low-temperature microwave annealing is utilized for the fabrication of dopant segregated Schottky barrier gate-all-around nanowire transistors. Low electron Schottky barrier of ytterbium silicide was combined with Phosphorus segregation to form metallic source/drain for high-performance N-channel nanowire transistors. Effects of microwave annealing on metal silicidation as well as dopants segregation are intensively examined by comparing with those using rapid thermal annealing. The minimum microwave power of 200% and processing time of 200 s can be used during annealing to minimize the thermal energy while retaining sufficient activation and silicidation. Experimental results show that the microwave annealing produce better electrical characteristics of dopant segregated Schottky barrier nanowire transistors, serving as a promising approach to fabricate metallic source/drain nanowire transistors for future 3D integration of CMOS technologies.

2D physics-based closed-form modeling of dopant-segregated Schottky barrier UTB MOSFETs

A 2D closed-form, analytical compact current model for long and short-channel Schottky barrier (SB) Multi-Gate MOSFETs is presented. The physics-based two-dimensional model for the electrostatic potential and electric field of a ultra-thin body (UTB) MOSFET is derived with the help of Poisson’s equation and the conformal mapping technique by Schwarz–Christoffel. Furthermore, simple closed-form current equations were derived by using analytical expressions for the tunneling and thermionic currents. Essential 2D effects on the currents are included in the model which are combined with diffusion effects in the channel region. A comparison of our 2D physics-based compact model is done versus measurement data for a dopant segregated fully-depleted Schottky barrier MOSFET.

Comparative study of dopant-segregated Schottky barrier germanium nanowire transistors

P-type Schottky barrier Ge nanowire transistors modulated with dopant segregated regions are proposed and studied. The impact of dopant segregated regions on device performance is simulated and investigated with numerical tools. It is revealed that dopant segregation is beneficial to increasing drive current and better utilizing nanowire channel. The OFF-state current is effectively suppressed with high dopant concentration, and the phenomena in the minimum current curves are carefully reinterpreted with carrier transport mechanisms. It is also shown that the dopant segregated regions with moderate length and high concentration can achieve high ON/OFF ratio and low subthreshold slope. Furthermore, we find that the subthreshold slope of long segregation length is insensitive to source/drain barrier heights, and that moderate segregation length helps to obtain lower subthreshold slope as channel length is scaled down.

Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on–off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices.

Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ∼40% and ∼20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes.

Vertical Silicon Nanowire Diode with Nickel Silicide Induced Dopant Segregation

Dopant segregated Schottky barrier (DSSB) and Schottky barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated using industry complemetary metal oxide semiconductor field effect transistor (CMOS) processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing steps on nickel silicide formation in the DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower off-current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also presented ideality factor much closer to unity and exhibited lower electron Schottky barrier height (ΦBn) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing sequence using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ∼5× and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to the 1-step DSSB VSiNW diode.

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits

In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX-δ) MOSFETs has been explored by extensive mixed-mode device/circuit simulations. It has been found that, the presence of partial buried oxide and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only suppresses the off-state leakage, short-channel effects, self-heating effect and the process induced threshold voltage variability but also improves the on-state drive current of the devices. Further, although switching energy in the CMOS inverter, NAND and NOR gates based on DSSB SOI and DSSB Pi-OX-δ MOSFETs is almost equal, static power dissipation and propagation delay in the logic gates based on DSSB Pi-OX-δ MOSFET are reduced by ∼75% and ∼20% respectively over the logic gates based on DSSB SOI device. Thus, employing partial buried oxide and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it a suitable candidate for nanoscale CMOS logic circuits.

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

In this paper, the impact of segregation layer density (NDSL) and length (LDSL) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the NDSL the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the LDSL the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a commonsource amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing NDSL and LDSL of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

In this paper, it has been shown that employing an underlap channel created by using the dual spacers in dopant-segregated Schottky barrier (DSSB) SOI MOSFET not only reduces the off-state leakage, short-channel effects and the parasitic overlap capacitances but also suppresses the variability induced by process fluctuations in the Schottky barrier height, dopant-segregation length and SOI film thickness of the device. However, the reduced effective gate voltage due to voltage drop across the underlap lengths also reduces the on-state drive current of the device. To alleviate this trade-off, a novel dual-k spacer underlap channel DSSB SOI structure has also been proposed in which the increased fringing electric field effect due to high-k inner spacer layer not only improves the on-state drive current but also reduces the off-state leakage current in both n-channel and p-channel devices. Despite the presence of high-k inner spacer layer increasing the fringing gate capacitance, the scalability in an optimized dual-k spacer underlap structure has improved by ∼60% and ∼35%, respectively over the conventional spacer overlap and underlap channel structures. In addition, the variability in an optimized dual-k spacer underlap structure has also been reduced by ∼50% and ∼30% respectively over the conventional spacer overlap and underlap channel structures. This clearly indicates that the proposed dual-k spacer underlap structure is a better choice for low-variability nanoscale CMOS logic circuits. The detailed fabrication flow of this novel device has also been proposed which demonstrates the use of conventional CMOS processes.

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at ID=5μA/μm and VDS=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at VDD=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ∼20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at VDD=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ∼10%, ∼35% and ∼25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.

Effect of Nickel Silicide Induced Dopant Segregation on Vertical Silicon Nanowire Diode Performance

ABSTRACTIn this work, Dopant Segregated Schottky Barrier (DSSB) and Schottky Barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated on p-type Si substrate using CMOS-compatible processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing processes on nickel silicide formation in DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower leakage current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also gave ideality factor much closer to unity and exhibited lower electron SBH (ΦBn) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ~ 5X and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to 1-step DSSB VSiNW diode.