Domino CMOS Logic Research Articles

Low power domino logic circuits in deep-submicron technology using CMOS

Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in deep sub-micron technology. This paper proposes a novel technique: Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic gates for the reduction in leakage power and improved noise performance. Two, four, eight and sixteen input OR gates are designed using existing and proposed techniques. These logic gates are simulated on the PTM 32 nm node using HSPICE (Level = 54) in CMOS technology at a clock frequency of 100 MHz. Simulation results are compared based on power consumption, propagation delay and unity noise gain. Simulation results show that proposed domino technique has a maximum power reduction of 59.47% as compared to the CSK-DL technique and maximum delay reduction of 44.6% as compared to the M-HSCD technique in CMOS technology.

Design and Comparative Analysis of Domino Logic Styles

Background/Objective: To design the AND, OR type circuits based on foot based and foot-less based gate domino logic and compare the results. Methods/Statistics: Nowadays VLSI circuits are expected to operate with low power, high speed, less area and noise tolerance. The major challenge in VLSI circuits is to obtain high performance. There are several digital logic techniques available viz. pseudo static CMOS, pass-transistor logic, complementary pass-transistor logic, GDI, dynamic CMOS logic, domino CMOS logic, which can be used to achieve high performance circuits. Findings: Static CMOS circuits have both pull down and pull up networks, but the disadvantage is, total number of transistors in the circuit is more. The dynamic logic circuits overcome the disadvantage of static complementary MOS. On the other side dynamic logic suffers from charge leakage, charge sharing and noise sensitivity, due to sub-threshold leakage current flow in the Pull Down Network (PDN), called stacking effect. When we scale down the technology, these effects will also get increased.Keywords: Footed, Foot-Less Domino, Power Dissipation

16-Bit Fast Addition Computation using Domino Logic

Objectives: A 16-bit carry look ahead adder is implemented in domino CMOS logic is presented in this paper. The proposed work comprises of two separate 8-bit carry chains. Statistical Analysis: This is evaluated using TANNER EDA tool. The schematics are drawn in s-edit, netlists are generated using T-spice and the waveforms are verified using waveform viewer or w-edit. Layouts can also be created using SDL (Schematic Drawn Layout), by importing netlist in L-edit. Findings: Due to the split carry chains in the adder, the speed of computation is increased, at the cost of area, when compared with ordinary carry look ahead adder. As we know that the use of domino logic reduces the power consumption, but as switching occurs many times power consumption is increased, that is the switching power of the system is increased. Applications: In VLSI system reducing the multipliers and increasing the adders is the main factor, thus in place of those adders if this split carry adders are used, the speed will be increased further.

Small‐swing domino logic based on twist‐connected transistors

A new small-swing domino logic that reduces the signal amplitude by adding twist-connected PMOS and NMOS transistors in the conventional domino logic is presented. The circuit lowers the voltage level of a logic `1' and increases the voltage level of a logic `0' while maintaining the logic threshold at half of the supply voltage. The output swing range of the proposed circuit can be modulated by varying the size of the twist-connected transistors and the load capacitance. The 32-bit ripple carry adders designed with the proposed circuit technique reduce power consumption by 37% and the power-delay product (PDP) performance by 43%, as compared with the power consumption and PDP performance of the domino CMOS logic. Thus, the proposed circuit effectively reduces power consumption with the use of the new small-swing domino logic.

New High-Speed Multioutput Carry Look-Ahead Adders

In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

Implementation of ALU Using Asynchronous Design

Power consumption has become one of the biggest challenges in design of high performance microprocessors. In this paper we present a design technique using GALs (Globally-Asynchronous Locally- Synchronous) for implementing asynchronous ALUs, which aims to eliminate the global clock. Here ALUs are designed with delay insensitive dual rail four phase logic and CMOS domino logic. It ensures economy in silicon area and potentially for low power consumption. This has been described and implemented in order to achieve a high performance in comparison with synchronous and available asynchronous design. Also simulation results, show significant reduction in the number of transistors as well as delay.

High-performance low-power dual transition preferentially sized (DTPS) logic

We present a dual transition preferentially sized (DTPS) logic that uses two separate paths - one for the fast propagation of low-to-high signal and the other for fast propagation of high-to-low signal. DTPS logic is suitable for multistage buffers and critical sections of datapaths requiring good noise immunity and low power dissipation while achieving high performance. We derived formulas to obtain optimal tapering factors of multistage buffers based on preferentially sized (PS) inverters, and implemented DTPS logic using the optimal tapering factors. We fabricated datapaths based on static CMOS logic, domino logic, and DTPS logic in 0.18-/spl mu/m technology. DTPS logic shows 15% and 16% improvements in performance and power dissipation, respectively, over domino, and 42% improvement in performance compared to static CMOS.

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method.

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

In this paper we present new strongly code-disjoint (SCD) and strongly fault-secure (SFS) checkers for the 2-out-of-3 and1-out-of-3 codes. They are implementedin Domino CMOS logic andtake into account a comprehensive fault model consisting of stuck-at, transistor stuck-open andtransistor stuck-on faults. The proposedcheckers are the first known SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers in the open literature that consider the above fault model without suffering from static power consumption.

CMOS LOGIC FAMILIES FOR VLSI DESIGN

In this paper, the investigation and evaluation of different stateof-the-art CMOS logic families, currently in use for VLSI design, are performed. These logic families are static CMOS logic, Pseudo-NMOS logic, Domino logic and Two-phase dynamic logic (TPDL). The main characteristics of these logic families, which are, power consumption, layout area and ease of implementation, are analyzed and compared. For the comparison among the different logic families, three basic logic gates are implemented using each of these logic families. The implemented gates are an Inverter, a 2-input NAND, and a 2-input NOR gates. The simulation is performed icing Tanner-Pro tools for different technologies starting from 1.6 urn to 0.25 um feature size at a power supply voltage (Vdd) of 5 volts. The technology parameters were extracted and measured from a fabrication lot by MOSIS SCN16 to SCNO25.

High-speed and low-power CMOS priority encoders

The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively. Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design with a simple look-ahead structure.

Reconfigurable Shift Switching Parallel Comparators

We present novel asynchronous VLSI comparator schemes which are based on recently proposed, reconfigurable shift switch logic and the traditional (precharged) CMOS domino logic. The schemes always produce a semaphore as a by-product of the process to indicate the end of domino process, which requires no additional delay and a minimal number of additional devices. For a large percentage of inputs the computations are much faster than traditional synchronous comparators due to the full utilization of the inherent speed of the circuits. Also the schemes are simple, area compact and stable.

BiCMOS domino: a novel high-speed dynamic BiCMOS logic

A new BiCMOS dynamic logic family is presented. The logic gates provide a significant speed-up over existing logic families, such as, CMOS, BiCMOS and dynamic CMOS for the same feature size. The proposed logic family provides a high drive capability to drive large loads at higher speeds compared with the CMOS domino logic family. The proposed logic family has power advantages, due to dynamic operation, compared with the conventional fully complementary CMOS and BiCMOS devices. It also has an area advantage compared with conventional BiCMOS gates. The proposed high-speed BiCMOS domino family provides speed improvement with existing feature size, using the existing fabrication technology. The novel high-speed dynamic BiCMOS logic implementations can significantly affect the speed of VLSI circuits including microprocessors, memories and signal processors.

Adiabatic pseudo-domino logic

A new logic structure, adiabatic pseudo-domino logic (APDL), which is the combination of adiabatic theory and CMOS domino logic is described. APDL circuits are compact, easy to cascade, and have outputs that are more stable than other adiabatic logic. Comprehensive circuit simulations show that APDL logic can recover over 80% of the energy dissipated in conventional static CMOS logic.

High speed CMOS POS PLA using predischarged OR array and charge sharing AND array

A family of four PLAs using triggered decoders charge sharing is presented. They can be classified into two types. In the front of the OR-AND array, the two types 1 and 2 use 1-b or 2-b triggered decoders, respectively. Type 1 is a single-phase dynamic CMOS POS (NOT-NOT)-(NOT-NOR)-(NOT-NOT) PLAs in a product of sums (POS) using CMOS domino logic in the OR array and charge sharing logic in the AND array. Type 2 is a single-phase dynamic CMOS POS OR-(NOT-NOR)-(NOT-NOT) PLA in a POS using predischarged OR gates like NMOS domino logic and charge sharing logic. By using charge sharing for the implementation of a cascaded AND array in types 1 and 2, and by using a triggered input technique to replace ground switches, faster PLAs that require lower power dissipation than the conventional fastest CMOS SOP (NOT-NOR)-(NOT-NOT)-(NOR-NOT) PLA in a sum of products (SOP) are achieved. By using triggered 2-b decoders on the input during the precharge time, the capacitance of an input minterm of a PLA can be minimized to reduce power consumption. >

High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b*16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2- mu m CMOS double-metal technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing for multiple faults in domino-CMOS logic circuits

The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view. >

Design optimization of JCMOS structures

JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure.

Errata to "Analysis and Design Optimization of Domino CMOS Logic with Application to Standard Cells"

Errata to "Analysis and Design Optimization of Domino CMOS Logic with Application to Standard Cells"

An improvement for Domino CMOS logic

Domino CMOS logic provides higher speed and easier testability compared with static and dynamic CMOS logic. The Domino CMOS logic gate with a conditional inverter can be used to alleviate the inversion problem inherent in the original Domino CMOS logic. It keeps the speed and testability of Domino logic while improving logic flexibility.