High-speed and low-power CMOS priority encoders

Abstract

The design of two high-performance priority encoders is presented. The key techniques for high speed are twofold. First, a multilevel look-ahead structure is developed to shorten the critical path effectively. Second, this look-ahead structure is realized efficiently by the NP Domino CMOS logic, and all the dynamic gates have a parallel-connected circuit structure. For high speed and low power at the same time, the series-connected circuit structure is adopted in the less critical paths to reduce the switching activity, but such a design needs to cascade two n-type dynamic gates directly resulting in the race problem. A special circuit technique is utilized to rescue this problem. Several 32-bit priority encoders are designed to evaluate the feasibility of the proposed techniques. The best new design realizes a three-level look-ahead structure, and it achieves 65% speed improvement, 20% layout area reduction, and 30% power reduction simultaneously as compared to the conventional design with a simple look-ahead structure.