Doherty Power Amplifier Research Articles

Dynamic behavioral modeling of RF power amplifiers based on decomposed piecewise machine learning technique

AbstractMulti-device radio frequency power amplifiers (PAs) often exhibit strongly non-linear behavior in combination with long-term memory effects, leading to an extremely challenging model development cycle. This paper presents a new, dynamic, behavioral modeling technique, based on a combination of the real-valued decomposed piecewise method and concepts from the field of machine learning. The underlying theory of the proposed modeling technique is provided, along with a detailed modeling procedure. Experimental results show that the proposed decomposed piecewise support vector regression (SVR) model leads to significant performance improvements when compared with standard SVR models for both single transistor and multi-transistor PAs. Different model thresholds are used to test the proposed model performance for both PA types. For the single-transistor PA, modeled using only one partition, an approximately 10 dB normalized mean square error (NMSE) reduction is seen when compared with the standard SVR model. For the same PA, when utilizing two partitions, the reduction improves to 14 dB. When applied to a multi-device Doherty PA, the NMSE between model and measurement data is −50 dB, representing more than 10 dB improvement compared with the standard SVR model.

Highly efficient and broadband continuous Doherty power amplifier using modified harmonic matching structure

Highly efficient and broadband continuous Doherty power amplifier using modified harmonic matching structure

High Efficiency Doherty Power Amplifier Using Dual-Adaptive Biases

A 60 GHz CMOS Doherty power amplifier (Doherty PA) is investigated in this work. Due to the absence of ideal current source in CMOS technology, a dual-adaptive biases scheme is utilized to realize Doherty operation. The efficiency enhancement is realized by providing the optimum biases to the carrier and peaking amplifiers according to the input power level. The input matching network is designed using adaptive power distribution network (APDN). Therefore, the RF power loss at low power level is minimized. The load modulation is realized without using phase-offset lines and any bulky impedance inverters such as transformers and inductors. As a result, optimum load impedances are achieved at each power levels while the chip size is very compact. Meanwhile, the layout sensitivity and on-chip EM problems can be mitigated. The proposed Doherty PA is designed and fabricated in 65 nm CMOS process. The measured result reveals 16.8 dBm power at output 1-dB gain compression point (OP $_{\text {1dB}}$ ). 17.5% and 9.5 % power added efficiency (PAE) are achieved at $\text {OP}_{\text {1dB}}$ and 6-dB output back-off level.

A Methodology and a Metric for the Assessment of the Linearizability of Broadband Nonlinear Doherty Power Amplifiers

This letter proposes a novel methodology and a metric for the assessment of the linearizability of broadband nonlinear power amplifiers (PAs). Validation of the proposed methodology and the proposed metric on two linearized Doherty PAs (DPAs) using digital predistortion (DPD) technique was carried out and it demonstrated the suitability and appropriateness of the new metric. Different from the iterative optimization procedure between the PA circuit design and the DPD algorithm compensation, the proposed method aims to provide a quantitative criterion on the PA linearizability based on its frequency-dependent amplitude modulation (AM)/AM and AM/phase modulation (PM) characteristics. To verify the effectiveness of the metric, two DPAs were characterized before and after a DPD-based linearization. The average correlation coefficients between the values of the metric and the adjacent channel power ratio after DPD were 0.8763 and 0.9156, and that between the values of the metric and the error vector magnitude after DPD were 0.8618 and 0.7200 for PA1 and PA2, respectively, indicating that the evaluation method and the linearizability metric can be used as a good measure to assess the linearizability of broadband PAs.

Pseudo-Doherty Load-Modulated Balanced Amplifier With Wide Bandwidth and Extended Power Back-Off Range

This article presents a novel architecture of load-modulated balanced amplifier (LMBA) with a unique load-modulation characteristic different from any existing LMBAs and Doherty power amplifiers (DPAs), which is named pseudo-Doherty LMBA (PD-LMBA). Based on a special combination of control amplifier (carrier) and balanced amplifier (peaking) together with proper phase and amplitude controls, an optimal load-modulation behavior can be achieved for PD-LMBA, leading to maximized efficiency over extended power back-off range. More importantly, the efficiency optimization can be achieved with only a static setting of phase offset at a given frequency, which greatly simplifies the complexity for phase control. Furthermore, the cooperations of the carrier and peaking amplifiers in PD-LMBA are fully decoupled, thus lifting the fundamental bandwidth barrier imposed on the Doherty-based active load modulation. Upon theoretical proof of these discoveries, a wideband RF-input PD-LMBA is physically developed using the GaN technology for experimental demonstration. The prototype achieves a highly efficient performance from 1.5 to 2.7 GHz, e.g., 58%-72% of efficiency at 42.5-dBm peak power and 47%-58% at 10-dB output back-off (OBO). When stimulated by a 10-MHz long term evolution (LTE) signal with a 9.5-dB peak-to-average power ratio (PAPR), the developed PD-LMBA achieves an efficiency of 44%-53% over the entire bandwidth at an average output power of around 33 dBm.

Input-Harmonic-Controlled Broadband Continuous Class-F Power Amplifiers for Sub-6-GHz 5G Applications

A comprehensive analysis is presented for investigating the effects of input nonlinearity on performance and broadband design of continuous-mode class-F power amplifiers (PAs). New time-domain waveforms are derived considering input and output harmonic terminations for continuous-mode class-F operation. The derived design equations show that the typical fundamental load design space of a continuous class-F PA must be reengineered in the presence of second-harmonic input nonlinearity to new design space in order to achieve optimum class-F PA performance versus varying second-harmonic load impedance. For the practical validation, the impacts of input nonlinearity on the performance of continuous-mode class-F PAs are first confirmed with pulsed vector load–pull (VLP) measurements on a low-power GaN 2-mm device. Second, a broadband high-power GaN 24-mm part is designed following the proposed theory with in-package input second-harmonic terminations targeting 1.75–2.3-GHz frequency band for the sub-6 GHz 5G high-power applications. Efficiency higher than 65% with peak power more than 53.2 dBm was maintained over the target frequency band, with excellent flatness. Third, a Doherty PA is implemented based on the designed GaN 24-mm part to evaluate the broadband performance with modulated stimuli. Using a multicarrier signal having an instantaneous bandwidth of 395 MHz, the average drain efficiency of the Doherty PA at 8-dB output back-off is higher than 44%, and the linearized adjacent channel power ratio (ACPR) is better than −52 dBc.

Analysis of load mismatch effect compensation in Doherty power amplifier

AbstractThis paper presents a theoretical and experimental analysis of the capabilities of the dual-input Doherty power amplifier (DPA) architecture to mitigate efficiency and output power degradations when used in a mismatched load environment. Following a simplified linear piecewise approach, an analytical demonstration is proposed to derive optimal radio frequency drives applied to the Auxiliary path of the DPA to restore power performances while avoiding large signal voltage clipping of active cells. The proposed analytical study is corroborated with harmonic balance simulated results of a C-band, 20-W GaN DPA prototype. The fabricated dual-input DPA prototype has been measured under 1.5-VSWR mismatch configurations to validate the proposed analysis.

Multiband Dual-Mode Doherty Power Amplifier Employing Phase Periodic Matching Network and Reciprocal Gate Bias for 5G Applications

This article presents a novel method to design the multiband Doherty power amplifier (DPA). It is illustrated that phase periodic matching networks (PPMNs) can be used as multiband impedance inverters, off-set elements, and phase compensators to realize multiband DPAs. Moreover, the number of Doherty operation bands can be further increased by employing the reciprocal gate biases. A six-band dual-mode DPA with 1.8-2.2-/3.9-4.3-GHz operation bands in Mode I and 1.52-1.72-/2.38-2.53-/3.67-3.82-/4.53-4.68-GHz operation bands in Mode II using commercial GaN transistors is designed and implemented to validate the proposed method. The fabricated DPA achieves 8.7-13.5-dB gain and 39.6-41.5-dBm peak output power at all the designed bands. Drain efficiency of 49.2%-54.5% and 42.2%-56.7% is measured at a 6-dB output back-off in Mode I and Mode II, respectively. When stimulated by a five-carrier 100-MHz OFDM signal with a 7.7-dB peak-to-average power ratio (PAPR), adjacent channel power ratio (ACPR) of better than -48.9 dBc can be obtained by the proposed DPA after digital predistortion with 35.5%-50.1% average drain efficiency at 1.65/1.95/2.45/3.75/4.1/4.6 GHz, respectively.

Bandwidth Enhancement of Doherty Power Amplifier Using Modified Load Modulation Network

A novel Doherty power amplifier (DPA) architecture with extended bandwidth is presented in this paper. A modified load modulation network is introduced to provide impedance condition required by the Doherty operation in a wide frequency range. Analytical parameter solutions of the proposed load modulation network and the related load modulation process are presented. A DPA with 2.80-3.55 GHz bandwidth utilizing commercial GaN transistors is implemented. The fabricated DPA attains a measured 9.3-11.1 gain and 43.0-45.0 dBm saturated power. 50.0-60.6% and 66-78% drain efficiency is obtained at 6 dB output power back-off and saturation throughout the designed band, respectively. Moreover, the back-off drain efficiencies are higher than 55% within 700 MHz bandwidth. When driven by a 6-carrier 120 MHz OFDM signal with 7.0 dB peak to average power ratio, the proposed DPA achieves adjacent channel leakage ratio of better than −50 dBc after digital pre-distortion (DPD) at 3.20 GHz with average efficiency of 53.3%.

Linearity Enhanced Harmonic-Modulated Impedance Inverter Doherty-Like Power Amplifier

In a conventional Doherty Power Amplifier (DPA), harmonic isolation is typically required between the two transistors to prevent them from modulating each other at harmonic frequencies. Normally, the current is clipped at saturation, which results in poor in-band non-linearity, e.g. IMD3. Hence, mutual harmonic interaction is desirable when properly used to prevent current clipping in the active devices, thus improving linearity. In this paper, for the first time, a linearity enhancement technique for Doherty-like power amplifier (DLPA) based on harmonic interaction is presented. The proposed DLPA achieves an excellent trade-off between efficiency and in-band linearity. For demonstration purposes, a DLPA prototype is devised based on two identical 6-Watts gallium nitride HEMTs (CGH 40006P). Within the frequency band of 1.75 to 2.45 GHz, the DLPA achieves a measured power added efficiency (PAE) of greater than 45.0% and 61.9% at 6 dB output back-off and saturation, respectively. An IMD3 below −30 dBc and a PAE of greater than 53% is achieved near saturation under a two-tone signal excitation.

Filtering Doherty power amplifier

At present, it is a trend in wireless communication to integrate conventional separate components into a single one for further miniaturisation and whole performance optimisation. In this study, a novel filtering Doherty power amplifier topology is proposed, which incorporates a bandpass power divider for power division. The power divider is characterised by third-order bandpass response and good out-of-band performance, and then it can purify the input spectrum for the whole amplifier. For demonstration, an example of this filtering Doherty power amplifier at 2.0 GHz was designed, fabricated and measured. The measured results show that at least 21 dB of the out-of-band suppression is obtained up to fourth harmonic for purifying the input spectrum. Meanwhile, high back-off efficiency is still retained for this filtering Doherty power amplifier.

Balanced-to-Doherty Mode-Reconfigurable Power Amplifier With High Efficiency and Linearity Against Load Mismatch

A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) is presented in this article, which is endowed with a unique capability of maintaining high linearity and high efficiency against load mismatch. The Doherty operation of this PA is based on a new Doherty PA (DPA) architecture configured from an ideal balanced amplifier, named quasi-balanced DPA (QB-DPA). This article, for the first time, analytically proves that the QB-DPA is functionally equivalent to a standard DPA. Most importantly, this new discovery enables PA reconfiguration between the Doherty and balanced modes. With the tunability implemented using a silicon-on-insulator (SOI)-based single-poledouble-throw (SPDT) switch, a reconfigurable B2D PA prototype using GaN technology is demonstrated at 3.5 GHz, exhibiting the state-of-the-art linear DPA performance in the nominal 50-Ω load condition. Specifically, the Doherty mode achieves a continuous-wave measurement efficiency of 70% and 54.5% at the maximum output power of 41.9 dBm and 6-dB power backoff, respectively. In the modulated long-term evolution (LTE) evaluation, the DPA exhibits -37-dB adjacent channel power leakage (ACPR) and 2.36% error vector magnitude (EVM) at the maximum rated power of 34.5 dBm while achieving a 42.4% efficiency. It is experimentally demonstrated that the Doherty (QB-DPA) mode is well resistant to load mismatch with high efficiency across a majority portion of the 2:1 voltage standing wave ratio (VSWR) circle, while the combination of Doherty and balanced modes can ensure a constantly linear performance of the B2D PA (e.g., 2.2%-5% of EVM) under the entire mismatch condition.

A Coupler-Based Differential mm-Wave Doherty Power Amplifier With Impedance Inverting and Scaling Baluns

Designing Doherty power amplifiers (PAs) at high millimeter-wave (mm-Wave) range remains a major challenge because most Doherty combiners at this frequency band are inefficient. To resolve this bottleneck, we analyze balun response under load variation and subsequently propose the Doherty PA architecture with impedance inverting and scaling baluns that perform active load modulation on differential PAs and delivers combined power to a single-ended load. At the PA output/input stage, instead of utilizing the transformer-based balun commonly used at RF and low mm-Wave frequencies, we explore the coupler-based balun to resonate out the device parasitic capacitance and achieve well-balanced differential to single-ended conversion at high mm-Wave frequencies. Based on the coupled-line theory and our analysis, we derive the [Y] matrix of the coupler-based balun and originate various solutions for baluns that can invert or scale impedance. From this derivation, we conceive a canonical form of impedance inverting baluns when the electrical length of coupled lines equals 45°. We also propose a close-formed solution for the coupler-based impedance scaling balun that is electrically equivalent to an idealistic transformer in series with a small inductance. We then combine the proposed impedance inverting and scaling balun structures to construct a Doherty network that exhibits desirable Doherty active load modulation and occupies a single-transformer footprint. On the active circuit design, we employ the adaptive biasing circuit for both driver and PA stages of the auxiliary PA to enhance the main and auxiliary cooperation. Using a 45-nm GlobalFoundries CMOS SOI process, we fabricate a proof-of-concept Doherty PA that demonstrates 20.1-dBm $P_{\mathrm {sat}}$ , 19.3dBm OP1,dB, 26% peak power-added efficiency (PAE), and 16.6% PAE at 7-dB power back-off (PBO) from OP1 dB at 60 GHz. Our results indicate a substantial PAE enhancement at PBO and a state-of-the-art modulation efficiency achieved when transmitting digital pre-distortion (DPD)-free 64-QAM-modulated signals.

Doherty PAs for 5G Massive MIMO: Energy-Efficient Integrated DPA MMICs for Sub-6-GHz and mm-Wave 5G Massive MIMO Systems

To accommodate growing user demand for faster data rates and extensive connectivity, modern wireless communication systems must evolve to support a sharply increasing number of subscribers, all requesting service at the same time. This trend encourages the broad application of multiple input/multiple output (MIMO) systems. In fact, MIMO techniques can increase data rates, coverage of service areas, and communication reliability without additional RFs. In recent proposals for 5G systems, the required separate RF chains in massive MIMO RF front ends can reach up to 256, with bandwidths of up to 800 MHz per RF chain [1], [2]. Massive MIMO is a critical technology that helps significantly in increasing network capacity and spectral efficiency, while reducing wireless network interference, ultimately improving the end-user experience.

Breaking the Bandwidth Limit: A Review of Broadband Doherty Power Amplifier Design for 5G

The Doherty power amplifier (DPA) has been extensively explored in the past and has become one of the most widely used power amplifier (PA) architectures in cellular base stations. The classical DPA suffers intrinsic bandwidth constrains which limit its application in future 5G wireless transmitters. In this paper, we present a comprehensive review of the DPA bandwidth enhancement techniques proposed in literature in order to provide a thorough understanding of the DPA's broadband design for high-efficiency 5G wireless transmitters. We elaborate on the main bandwidth limitation sources and provide circuit design insights. We then follow with an overview of bandwidth enhancement techniques developed for the DPA, including modified load-modulation networks, frequency response optimization, parasitic compensation, post-matching, as well as distributed DPA, dual-input digital DPA, transformer-based power-combining PA, and transformer-less load modulated PA architectures. Furthermore, challenges and design techniques for integrated circuit (IC) implementation of broadband DPAs are discussed, including a review of circuits developed in CMOS, SiGe, and GaN processes, and operating in RF and mm-Wave frequencies.

Analysis and design of output matching network for Doherty power amplifiers

In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power amplifier is designed and measured. The operating frequency is from 1.75 to 1.95 GHz with the saturated output power of 43.5 dBm to 44.2 dBm. The measured peak drain efficiency is 58.8% to 71.7% and the 6 dB back-off drain efficiency is 50.9% to 61.4%.

Design of high-efficiency compact Doherty power amplifier with harmonics suppression and wide operation frequency band

A novel Doherty power amplifier (DPA) using a novel power divider with harmonics suppression and size reduction is proposed. The designed power divider suppresses eight unwanted harmonics. Moreover, the proposed divider reduces the circuit size and only occupies 41% in comparison with conventional divider. In the DPA structure two elliptical resonators are used instead of two long λ/4 transmission lines to size reduction. The AB and C classes power amplifiers are exploited as main and auxiliary amplifiers. The proposed DPA has good specifications such as wide bandwidth from 500 MHz to 1900 MHz with a fractional bandwidth of 116%. The DE, PAE and gain parameters of the designed DPA are 76%, 71%, and 19 dB, respectively.

Envelope emulation

Researchers from the UK present a novel characterisation system that is capable of emulating a complete envelope tracking power amplifier (ET-PA) environment around a microwave power transistor. The system achieves this by using modulated impedance synthesis and a dynamic supply voltage generation, as well as industry-standard modulated signals and digital pre-distortion. The authors believe that the system will be of use to designers of ET-PAs, allowing more complete investigation of the performance of ET-PAs in realistic modulated and load impedance conditions. As communication systems evolve to transmit ever-larger volumes of data, including the ongoing roll-out of 5G worldwide, we will need to develop more advanced modulation schemes to satisfy the rampant growth and to improve spectral efficiency. Whilst new modulation schemes offer higher data throughput levels, they are characterised by high peak-to-average power ratios (PAPRs). Power amplifiers (PA) are the major power consumer in mobile communication systems, and thus several power amplifier architectures have been proposed to improve average PA efficiency, including the Doherty PA and envelope tracking (ET). Authors (right to left) Sattam Alsahali, Alexander Alex,Dr. Jonathan Lees and Dr. Peng Chen. Set-up of the present work. Average PAE for 28 V fixed bias (blue solid contours) and for ET (green dotted contours). ET works by rapidly changing the supply voltage of the PA in response to the input signal, providing low supply voltage for low powers and vice versa. Whilst ET presents itself as a strong candidate for a wide range of applications due to its potential to support both multimode and multiband operations, the design of the ET-PA presents an array of challenges relating to optimisation of and interaction between involved sub-systems, in particular the radiofrequency (RF) potential of the ET-PA. Characterising the performance of a radiofrequency power amplifier (RFPA) and optimising its performance as early as possible within the ET environment is highly desirable. Load-pull, the colloquial term for the process of systematically varying impedance presented to a device under test, is a robust approach commonly utilised at the beginning of the design phase of an RFPA to characterise the device's performance at fundamental and harmonic frequencies, typically in terms of output power, efficiency, gain and linearity. The work presented by Alsahali et al. is the first work that combines a fast, modulated load-pull system (known as the Mesuro RAPID system) and digital pre-distortion, producing a powerful ET characterisation bench. Achieving this ET characterisation bench wasn't easy, the team had to combine and synchronise a number of different systems. In particular, the efficiency measurement and the time alignment between the RF signal and the tracking signal were especially challenging to characterise. Despite the challenges, the team's Letter shows that they ultimately succeeded in pulling together myriad subsystems to produce a highly useful package. The authors hope that their proposed system will be useful for the future design of ET-PAs by providing a powerful emulation tool. This first example only allows for fundamental load pull, in order to fully investigate the potential of the new measurement architecture, the ability to incorporate harmonics, specifically the 2nd and 3rd harmonics (significant in realising highly efficient PA modes of operation), will be highly beneficial. In addition, it was found that the modulation bandwidth of the Mesuro RAPID load-pull system is limited to 40 MHz. A 5G system will require at least 100 MHz to fully characterise the nonlinearity of RFPAs, which requires at least five times the modulation bandwidth. The group has already begun working on these bandwidth enhancements - watch this (ever expanding) space.

Power‐efficient full‐duplex K/Ka‐band phased array front‐end

This study presents the first monolithically integrated full-duplex front-end for K/Ka satellite communication phased arrays. A 0.25 μm SiGe:C BiCMOS process was used to develop the integrated circuit. The receive and transmit channels are united into a common port through a novel duplexer. For each RF channel, the bias currents, the active channels and the power amplifier operation mode can be controlled through a serial bus. Amplitude and phase control are provided with fine granularity (65,536 states). In transmit mode, each channel provides 37.3 dB of gain with 12.9 dBm output power at 1-dB compression. In receive mode, 33.7 dB gain is measured with a noise figure of 3.2 dB. The amplitude/phase root-mean-square errors within the transmit (29.5–30.8 GHz) and receive (19.7–21 GHz) bands are below 0.7 dB/ 6.4 ° and 0.26 dB/ 1.1 ° , respectively. The chip occupies 1.64 × 3.5 m m 2 and it consumes 81 and 15.5 mW per transmit and receive channels, respectively. The use of a Doherty power amplifier with a novel dynamic adaptive bias circuit led to a 31% reduction of the total dc array power consumption.

A high-efficiency Doherty Power Amplifier for wireless base stations

ABSTRACT This paper presents a new high-efficiency two-way Doherty Power Amplifier (DPA) with a modified output matching structure for Wideband Code Division Multiple Access (W-CDMA) low-to-medium power base station applications. A blended design is proposed using the symmetrical topology of equal rated power amplifying devices with unequal output impedances for the carrier and peaking amplifier to achieve enhanced efficiency and desired linearity in 1900 MHz band. The proposed output circuit modifications encompass the usage of parasitic capacitor compensation technique for the carrier amplifier, optimum offset line along with the Doherty combiner to achieve high efficiency over 6 to 10 dB extended range of back-off operation. The measured results of the DPA demonstrate a Power Added Efficiency (PAE) of more than 49.9% at +34 dBm W-CDMA signal power, which is between 8 and 8.5 dB back-off from the peak power level of 42.2 dBm. The DPA has a large signal power gain of 13 dB at 1960 MHz. Further, the PAE is 39.5% and linearised Adjacent Channel Power Ratio (ACPR) is −46.2 dBc, both at 10 dB back-off from peak power. In these back-off power levels, this implementation provides significant efficiency improvement using symmetrical devices and with excellent linearity.