High Efficiency Doherty Power Amplifier Using Dual-Adaptive Biases

Abstract

A 60 GHz CMOS Doherty power amplifier (Doherty PA) is investigated in this work. Due to the absence of ideal current source in CMOS technology, a dual-adaptive biases scheme is utilized to realize Doherty operation. The efficiency enhancement is realized by providing the optimum biases to the carrier and peaking amplifiers according to the input power level. The input matching network is designed using adaptive power distribution network (APDN). Therefore, the RF power loss at low power level is minimized. The load modulation is realized without using phase-offset lines and any bulky impedance inverters such as transformers and inductors. As a result, optimum load impedances are achieved at each power levels while the chip size is very compact. Meanwhile, the layout sensitivity and on-chip EM problems can be mitigated. The proposed Doherty PA is designed and fabricated in 65 nm CMOS process. The measured result reveals 16.8 dBm power at output 1-dB gain compression point (OP $_{\text {1dB}}$ ). 17.5% and 9.5 % power added efficiency (PAE) are achieved at $\text {OP}_{\text {1dB}}$ and 6-dB output back-off level.