Dit Values Research Articles

Achieving Near‐Ideal Subthreshold Swing in P‐Type WSe2 Field‐Effect Transistors

AbstractThe pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.

Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer

This study reports a self-induced ferroelectric Ge-doped HfO2 (Ge:HfO2) thin film through interface reactions. In the first experiment, three treatments for forming interfacial layer (IL) were discussed through TiN/2-nm-thick Al2O3/2-nm-thick Ge:HfO2/GeO2/Ge metal-ferroelectric-insulator-semiconductor capacitors. The remnant polarization (Pr), leakage current, and interface trap density (Dit) were compared to select the most appropriate IL treatment. The results show that the in-situ ozone treatment under the standard atomic layer deposition process had the second highest 2Pr value as well as lower Dit values. Next, the thicknesses of Al2O3/Ge:HfO2 would be changed to 4 nm/2 nm and 3 nm/3 nm to investigate the ferroelectricity and leakage current. Although the 3-nm-thick Al2O3/3-nm-thick Ge:HfO2 shows a lower 2Pr value, the leakage current is much lower than 2-nm-thick Al2O3/2-nm-thick Ge:HfO2. The self-induced ferroelectric 3-nm-thick Ge:HfO2 thin film was then applied to fabricate Ge stacked nanowires gate-all-around field-effect transistor. The results show a steep subthreshold slope of 58 mV/dec for pFET and on-off current ratio > 105 and have high potential in low-power IC applications.

Optimizing interface properties of HfO2/Si0.73Ge0.27 gate stacks through sulfur passivation and post-deposition annealing

This paper presents a comprehensive exploration of low interface trap density (Dit) in HfO2/Si0.73Ge0.27 metal-oxide semiconductor (MOS) capacitors achieved through sulfur passivation and post-deposition annealing (PDA). Our investigation revealed that devices subjected to sulfur passivation and PDA exhibit noteworthy reductions in Dit and hysteresis. Specifically, a low Dit value of 1.2 × 1011 eV−1 cm−2 has been achieved at Ei–0.1 eV for the SiGe MOS device. The observed enhancement in interface properties can be attributed to two key factors: the reduction of the GeOx concentration in the interfacial layer (IL) by sulfur passivation on the SiGe surface and the IL densification with stoichiometric oxygen during PDA.

Amorphous Carbon Monolayer: A Novel and Effective Interlayer for Metal/Oxide Interface

We investigate the effect of one-atom thick Amorphous Carbon Monolayer (ACM) as an interfacial layer (IL) for high-k/Ge MOS structure, with the aim of suppressing the dangling bonds on the Ge surface and reducing the interfacial defects between high-k oxide and Ge layers. The frequency-dependent C-V characteristics indicated that the ACM layer eliminates the weak inversion response resulting in a steeper C-V slope and an increase in accumulation capacitance. The G-V analysis further confirmed the lower density of interface traps in the ACM layered device. The Dit values were extracted as 1.2×10¹¹ cm⁻²eV⁻¹ for Al2O3/ACM/Ge structure, which is almost two orders of magnitude lower than that of the Al2O3/Ge structure without the ACM layer. The observed improvements are attributed to the effective blocking role of the ACM interlayer against the in-diffusion of oxygen and out-diffusion of Ge and the suppression of dangling bonds at the Ge surface. Our findings suggest that the Al2O3/ACM/Ge structure exhibits superior electrical quality with lower hysteresis and interface charge trapped density, which has important implications for the development of high-performance ultra-small-scale devices based on Ge substrates.

Different temperature dependence of mobility in n- and p-channel 4H-SiC MOSFETs

The impact of interface state density (D it) near the conduction band edge (E C) and the VB edge (E V) on the field-effect mobility (μ FE) of NO- and N2-annealed n- and p-channel MOSFETs was investigated. With lowering the temperature, μ FE of n-channel MOSFETs decreased whereas μ FE increased in p-channel devices. Despite the comparable D it values near E C and E V, p-channel MOSFETs have less trapped carriers due to a deeper surface Fermi level caused by the larger effective masses of holes, resulting in smaller Coulomb scattering, and this may cause the different temperature dependence of μ FE in n- and p-channel MOSFETs.

Low-frequency noise in quasi-ballistic monolithic Al–Ge–Al nanowire field effect transistors

In this work, Al2O3-passivated, monolithic, and crystalline Al–Ge–Al heterostructure nanowire field effect transistors (FETs) with Ge channel lengths ranging from 18 to 826 nm are analyzed from a low-frequency noise perspective. 1/f and random telegraph noise (RTN) are analyzed in an accumulation mode, where the hole channel is formed by applying a back-gate potential VG. The normalized power spectral density of drain current fluctuations of 1/f noise (SID/ID2) at medium currents follows nearly an 1/ID trend. 1/f noise is analyzed within both the mobility and carrier number fluctuation models (MFM and CNFM), respectively. Taking the MFM into account, the Hooge noise parameter α spreads in the interval of 1.5 × 10−4 to 4 × 10−2, with lower values for shorter devices. Using the same data and the CNFM, the density of interface states Dit in the Al2O3/GexOy/Ge system was estimated using the transconductance extracted from the quasi-static transfer I/V characteristics. The extracted Dit values range from 5 × 109 to 3 × 1012 cm−2 eV−1. Contact noise has also been observed in some devices at high currents. RTN analyzed in time domain exhibits a relative RTN amplitude in the 0.3%–20% range. Capture and emission time constants as a function of VG exhibit a typical behavior for metal oxide semiconductor FETs. The extracted noise parameters are comparable with Ge and III–V nanodevices of top-down and bottom-up technologies.

Fabrication and characterization of germanium n-MOS and n-MOSFET with thermally oxidized yttrium gate insulator: Formation of underlying germanium oxide and its electrical characteristics

A high-quality insulating film on germanium is essential for germanium applications. In this study, we oxidized metal yttrium at 500–550 °C to generate an yttrium oxide (Y-oxide) layer on germanium. According to transmission electron microscopy images, Y-oxide comprised three layers, which were Y2O3, YGeO3, and GeOx from the top side. n-Type metal-oxide-semiconductor (n-MOS) capacitors and n-type MOS field-effect transistors (n-MOSFETs) with the Y-oxide gate insulator showed typical electrical characteristics. The n-MOS capacitor with the Y-oxide gate insulator had a lower interface state density (Dit) and border trap density (Nbt) than the n-MOS capacitor with a thermally oxidized GeOx insulator, suggesting that defects were terminated by Y atoms in the GeOx layer and GeOx/Ge interface. In contrast, the Dit–energy distribution and Nbt temperature dependence of the Y-oxide gate insulator were similar to those of the GeOx gate insulator, indicating that the defect signals originated in GeOx underlying YGeO3. The structural analysis showed that the temperature of metal yttrium oxidation affected only the GeOx thickness. Therefore, adjusting the conditions of metal yttrium oxidation may produce Y-oxidized gate stacks with a thinner GeOx layer or even direct contact of YGeO3 and Ge, which may result in different Dit values, Nbt values, and Nbt–temperature trends.

Effect of film stress on different electrical properties of PECVD grown SiNx films and its bilayer structures: A study of Si surface passivation strategy

The prevalence of stress during thin film deposition has a substantial influence on the surface passivation of CMOS image sensors (CIS). Our present research thoroughly addresses the effect of film stress on minority carrier lifetime and interface trap density (Dit) of as-deposited and forming gas annealed (FGA, 5% H2, 400 °C for 30 min) SiNx films and their bilayer structures. In this study, plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) techniques were utilized to synthesize SiNx and SiNx/(top) Al2O3 bilayer structures. After FGA, the minority carrier lifetime and Dit values for 50 nm-SiNx (1607 μs, 7 × 1011 cm−2eV−1), 30 nm-Al2O3 (2670 μs, 7 × 1011 cm−2eV−1), 7 nm-SiNx/30 nm-Al2O3 (1750 μs, 6 × 1011 cm−2eV−1) and 50 nm-SiNx/30 nm-Al2O3 (2300 μs, 34 × 1011 cm−2eV−1) were found. Our statistical analysis indicates that the stress in the SiNx/Al2O3 bilayer structures introduces defects in the films. This affects the carrier lifetime along with Dit values and hence degrades CIS performance. Further, we also performed a stress simulation of SiNx films which corroborated with the overall analysis. We hope that this work facilitates a better understanding of the stress effect on the surface passivation of CIS applications.

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe2 Semiconductor Devices.

Palladium diselenide (PdSe2), as an emerging two-dimensional (2D) layered material, is gaining growing attention in nanoelectronics and optoelectronics due to its thickness-dependent band gap, high carrier mobility, and good air stability. However, its asymmetric pentagon structure is inclined to breed defects. Herein, the intrinsic Se vacancy-induced trap states and their influence on the hopping transport in PdSe2 are systematically investigated. We provide direct evidence that Se vacancies exist in the fresh PdSe2 samples, which results in the localized trapping states inside the band gap. For the few-layer PdSe2, at 77 K, the trap density (Dit) near the midgap is about 2.2 × 1013 cm-2 eV-1, whereas at 295 K, the Dit value increases to ∼7.1 × 1013 cm-2 eV-1. By comparison, the multilayer PdSe2 shows nonobvious temperature-dependent trap behaviors with almost unchanged Dit values of ∼8.1 × 1012 cm-2 eV-1 at midgap in the temperature range between 77 and 295 K. Thus, trap states in the few-layer PdSe2 are more vulnerable to temperature effect. Transport measurements demonstrated that both few-layer and multilayer PdSe2 field-effect transistor (FET) devices show n-type dominant ambipolar behaviors. The electron mobility in the multilayer PdSe2 FET is nearly 15-fold higher than that in the few-layer PdSe2 FET at 315 K, probably owing to the decreased effective mass and suppression of charge impurity scattering in the thicker channel material. However, both FET devices exhibit variable-range hopping over a temperature range from 77 to 240 K and thermally activated hopping at temperatures above 240 K. The hopping transport mechanism is strongly associated with the Se vacancy-induced localized states with poor screening and strong potential fluctuations. This study reveals the important role of structural defects in tailoring and improving the charge transport properties of PdSe2.

Nitrogen Annealing As a Sustainable Method for Interface Trap Passivation in 4H-SiC Mosfets

Silicon Carbide (4H-SiC) has emerged as a leading wide band gap semiconductor for high-power, high-temperature applications1. 4H-SiC metal-oxide semiconductor-field-effect transistors (MOSFETs) have lower power dissipation compared to silicon, allowing for low-noise and high-efficiency all-electric vehicle drives, fast-charging stations, solar inverters, and more. While these devices provide substantial advancements for next-generation energy efficient power systems, 4H-SiC may also offer additional functionality in the form of integrated circuits (ICs) at high temperatures (>300 °C). Because of its high noise immunity and low static power consumption, lateral complementary-metal-oxide-semiconductor (CMOS) IC technology in 4H-SiC is desirable for large-scale integration2. This technology necessitates the use of both n- and p-channel MOSFETs that can operate at high temperatures.Despite the advances of 4H-SiC MOSFETs, the high density of interface states (Dit) at the 4H-SiC/SiO2 interface prevents reaching full potential resulting in high channel resistance and low mobility. Alternatives to nitric oxide (NO) annealing, the most common method adopted to reduce Dit in 4H-SiC3,4, are actively sought due to its toxicity and relatively expensive cost. Annealing in pure nitrogen (N2)5,6 at high temperatures (1400 °C-1600 °C) has been recently demonstrated promising results for 4H-SiC MOSFET processing. In this work, we report Dit measurements consistent with [6] and attempt to correlate the nitrogen areal densities of the near interfacial regions with the Dit for high temperature N2 annealing processes compared to NO. In our study, metal oxide semiconductor capacitors were fabricated on p- and n-type 4H-SiC epitaxial layers. Gate oxides were thermally grown at 1150 °C for 10 h in dry O2 resulting in a ~ 60 nm thick oxide layer. Selected samples are then annealed in flowing N2 at high temperatures (1400 °C, 1 h; 1450 °C, 1 h; and 1500 °C, 30 minutes or 1 h) or NO (1175 °C, 2 h). X-ray photoelectron spectroscopy (XPS), carried out after etching the oxide, indicates that the amount of nitrogen at the interface due to high temperature N2 annealing is ~ 4 × higher than NO annealed devices. Simultaneous high frequency (100 kHz)- low frequency CV was performed to extract interface trap densities (Dit) for each process and compared at room temperature (27 °C) with reference 1175 °C, 2 h NO annealed samples. The comparison reveals that, N2 annealing at 1500 °C for 30 minutes with a flow rate of 3 LPM results in Dit values comparable to NO annealing across the bandgap. Moreover, nitrogen annealing is more effective in reducing Dit near the valence band than NO annealing, while the opposite is true close to the conduction band-edge, consistent with previous reports [6] and observed in atomistic models of these interfaces using the density functional theory7. Nitrogen annealing also decreases the positive fixed charges at the interface of p-type 4H-SiC and SiO2, as evidenced from the flat band voltage comparison. The oxide breakdown voltage for the devices made with 1500 °C N2 annealing was similar to that of NO annealed devices. XPS analysis of the N2 annealed devices, their behavior under high temperature and bias, and their potential to substitute NO will be further discussed.The authors gratefully acknowledge the support from the National Renewable Energy Laboratory/ US Department of Energy sub-contract NREL-AHL-9-92362-01.

(Invited) Thin Epitaxial Single-Crystal Si on Sige Followed By in-Situ Deposition of High-k Dielectrics – Novel Gate Stacks for Achieving Extremely Low Dit and Highly Reliable SiGe MOS

Silicon-germanium (SiGe) is replacing silicon (Si) as the channel layer for the p-type metal-oxide-semiconductor (pMOS) in the aggressively scaled complementary MOS (CMOS) technology. Many research efforts involving SiGe gate stacks have resulted in the attainment of low interfacial trap densities (Dits). Si-passivated SiGe gate stacks are the most promising method to achieve both low Dit and high device reliability. However, regardless of the growth methods, most publications reported the pileup of Ge atoms on top of the grown Si even after extensive treatments. The subsequent process in forming gate stacks, including oxidation, inevitably caused the segregated Ge to form GeOx, leading to degradation of the interfacial quality of the gate stacks.We have used molecular beam epitaxy (MBE) to grow thin single-crystal Si of 0.79nm thickness (six MLs) epitaxially on epi-Si1-xGex(001) under ultra-high vacuum (UHV). Different from its counterpart of chemical vapor deposition (CVD), MBE enables epi-Si growth on Ge at growth temperatures below 300 °C. The measurements using reflection high-energy electron diffraction (RHEED), high-resolution synchrotron radiation X-ray diffraction (HR-XRD), and the scanning transmission electron microscopy with high-angle annular-dark-field (STEM-HAADF) have revealed high crystallinity of the epi-Si, the Si1-xGex layers and abrupt interfaces of the high-k/epi-Si/Si1-xGex layers. Moreover, our unique capability of epi growth/analysis enabled the study of the electronic surface structures of epi-Si/epi-Ge using in-situ high-resolution synchrotron radiation photoemission spectroscopy (SRPES) via a portable sample transfer station under UHV. We have used SRPES to demonstrate that the as-grown Si1−xGex(001)-2×1 surfaces with Ge content ranging from 0.1 to 0.9 are all terminated with buckled Ge–Ge dimers, and the surface electronic structure is similar to that of epi-Ge(001)-2×1. The direct deposition of epi-Si on as-grown SiGe removed the top buckled Ge-Ge dimers, which diffused into the epi-Si and some segregated to the top of the Si. As a result, the topmost layer beneath the epi-Si was 1 ML of Ge, and the interfaces of high-k/epi-Si/Si1−xGex are similar to those of the high-k/epi-Si/Ge. Again, the hetero-interfaces of our gate dielectrics are different from those grown using CVD.The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3 - 6) × 1011 eV-1cm-2 in these high-k/epi-Si/Si1-xGex samples. The minimum Dit values remained at 3 × 1011 eV-1cm-2 regardless of the Ge content, demonstrating the effective passivation of the low-temperature deposited epi-Si. The limited Ge segregation during the low-temperature growth of epi-Si may attribute to the attainment of the low Dit values. We have benchmarked the minimum Dit (Dit, min) of our work with other state-of-the-art SiGe gate stacks. The Dit,min values from the other efforts increased with increasing Ge content, which may be caused by the GeOx formation that was difficult to control in the high-Ge-content (HGC) Si1-xGex.The effective charge sheet densities for the Si1-xGex gate stacks were extracted via examination of capacitance-voltage (C-V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors. We have attained very high acceleration factors of 8-12, indicating high reliability of the HfO2/epi-Si/Si1-xGex pMOS gate stacks.Furthermore, we have used a scavenging method, consisting of a cyclic process of an O2 exposure followed by a UHV annealing, to eliminate the segregated and diffused Ge in epi-Si before high-k deposition. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in-situ annealing at 500 °C under UHV moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeOx, but with a minimal amount of segregated Ge.

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer.

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

A quantitative approach for trap analysis between Al0.25Ga0.75N and GaN in high electron mobility transistors

The characteristics of traps between the Al0.25Ga0.75N barrier and the GaN channel layer in a high-electron-mobility-transistors (HEMTs) were investigated. The interface traps at the Al0.25Ga0.75N/GaN interface as well as the border traps were experimentally analyzed because the Al0.25Ga0.75N barrier layer functions as a dielectric owing to its high dielectric constant. The interface trap density Dit and border trap density Nbt were extracted from a long-channel field-effect transistor (FET), conventionally known as a FATFET structure, via frequency-dependent capacitance–voltage (C–V) and conductance–voltage (G–V) measurements. The minimum Dit value extracted by the conventional conductance method was 2.5 × 1012 cm−2·eV−1, which agreed well with the actual transistor subthreshold swing of around 142 mV·dec−1. The border trap density Nbt was also extracted from the frequency-dependent C–V characteristics using the distributed circuit model, and the extracted value was 1.5 × 1019 cm−3·eV−1. Low-frequency (1/f) noise measurement provided a clearer picture of the trapping–detrapping phenomena in the Al0.25Ga0.75N layer. The value of the border trap density extracted using the carrier-number-fluctuation (CNF) model was 1.3 × 1019 cm−3·eV−1, which is of a similar level to the extracted value from the distributed circuit model.

(Invited) Study of HfO2-Based High-k Gate Insulators for GaN Power Device

Gallium nitride (GaN) high-electron-mobility transistor and vertical GaN devices with metal-oxide-semiconductor (MOS) structure have been widely investigated to suppress leakage currents for applications associated with high power and high frequency [1-3]. Metal oxide (High-k) with a high dielectric constant (k)-value have been employed instead of SiO2 from the viewpoint of increasing the physical thickness [4, 5]. HfO2-based materials including HfO2, HfSiOx and HfAlOx are the candidate materials because of its relatively large bandgap (~6.5 eV) and a high k value (> 13) [6-9]. These films for transistor applications are typically fabricated using atomic layer deposition (ALD) because ALD is compatible with semiconductor fabrication process and has a big advantage of conformal film fabrication on three-dimensional structure. In this study, we report comparison of characteristics among HfO2, HfSiOx and HfAlOx gate insulators of GaN MOS capacitors.Pt-gated n-GaN MOS capacitors with HfO2, HfSiOx and HfAlOx gate insulators were prepared as follows. A single HfO2 layer, (HfO2)m/(SiO2)n and (HfO2)m/(Al2O3)n nanolaminate layers were deposited on n+-GaN/n-GaN epilayer by plasma-enhanced ALD at 300°C. The m/n ratio was kept at 2/1. Next, PDA was carried out at 800°C in N2. HfSiOx and HfAlOx films were formed from (HfO2)m/(SiO2)n and (HfO2)m/(Al2O3)n nanolaminate after PDA, respectively. The thicknesses of these films were ~24 nm. Finally, Pt gate electrode was deposited on gate insulator and Pt/Ti ohmic contact was deposited on the n-GaN substrate.The HfSiOx and HfAlOx films had an amorhous structure while HfO2 film had a polycrystalline structure after PDA at 800°C using transmission electron microscopy and electron diffraction pattern analysis. The HfO2 capacitor exhibited a small breakdown electric field (EBD) value of 2.6 MV/cm, defined at a current density of 1.0 × 101 A/cm2, because leakage currents easily flow along grain boundaries of the polycrystalline structure. On the other hand, the EBD values of the HfSiOx and HfAlOx capacitors increased up to 8.5 MV/cm. From capacitance-voltage measurements, the estimated k values of the HfO2, HfSiOx and HfAlOx films were 17.7, 17.2 and 13.5, respectively, as expected. The flatband voltage hysteresis (620 mV) of the HfO2 capacitor was much larger than those (~10 mV) of the HfSiOx and HfAlOx capacitors, indicating that the number of charge trapping/detrapping sites and frequency responsive defects was significantly decreased in the HfSiOx and HfAlOx capacitors. No frequency dispersion of the HfSiOx and HfAlOx capacitors were observed while the HfO2 capacitor showed a large frequency dispersion. The interface state density (Dit) values at Ec - E = 0.25 eV which estimated using the conductance method of the HfSiOx (~1 × 1011cm-2V-1) and HfAlOx (4.4 × 1011cm-2V-1) capacitors were one magnitude lower than that of the HfO2 capacitor (3.1 × 1012cm-2V-1), indicating that the electrical defects at n-GaN/HfSiOx and n-GaN/HfAlOx interfaces were much less than that of the n-GaN/HfO2 interface.We conclude that the HfSiOx and HfAlOx were the attractive materials as gate insulator because of amorphous structure, higher k, relatively low Dit, and high Ebd.This work was supported by JSPS KAKENHI (Grant No. JP20H02189). A part of this work was also supported by the MEXT “Program for research and development of next-generation semiconductor to realize energy-saving society.” Program Grant Number JPJ005357. The authors wish to thank Dr. A. Ohi, Dr. N. Ikeda, and the members of the nanofabrication group of the National Institute for Materials Science for their support during this study.[1] M. Kodama et al., Appl. Phys. Express 1, 021104 (2008).[2] Z. Yatabe et al., J. Phys. D: Appl. Phys. 49, 393001 (2016).[3] T. Oka et al., Appl. Phys. Express 8, 054101 (2015).[4] T. Hashizume et al., Appl. Phys. Express 11, 124102 (2018).[5] T. Kikuta et al, J. Vac. Sci. Technol. A 35, 01B122 (2017).[6] T. Nabatame et al., Appl. Phys. Express 12, 011009 (2019).[7] E. Maeda et al., Microelectron. Eng. 216, 111036 (2019).[8] R. Ochi et al., AIP Advances 10, 065215 (2020).[9] S. Miyazaki et al., ECS Trans. 92, 11(2019).

Study of interface trap density of AlOxNy/GaN MOS structures

GaN metal–oxide–semiconductor structures were fabricated by atomic layer deposition of aluminum oxynitride thin films on bulk GaN substrates with c-, a-, and m-plane surfaces. Capacitance–voltage measurements ranging from 5 kHz to 1 MHz were conducted at room temperature. The interface trap number density (Nit) and interface trap level density (Dit) of the devices were extracted. A Nit of less than 2 × 1011 cm−2 and a Dit of less than 2 × 1011 cm−2 eV−1 were obtained on the a-plane and m-plane samples. Nit and Dit values were larger for c-plane samples, with the largest interface trap density observed on the c-plane sample with the highest dislocation density. The different Nit and Dit values can be attributed to different dislocation densities and dangling bond densities among different samples.

Firing stability of tube furnace‐annealed n‐type poly‐Si on oxide junctions

AbstractStability of the passivation quality of poly‐Si on oxide junctions against the conventional mainstream high‐temperature screen‐print firing processes is highly desirable and also expected since the poly‐Si on oxide preparation occurs at higher temperatures and for longer durations than firing. We measure recombination current densities (J0) and interface state densities (Dit) of symmetrical samples with n‐type poly‐Si contacts before and after firing. Samples without a capping dielectric layer show a significant deterioration of the passivation quality during firing. The Dit values are (3 ± 0.2) × 1011 and (8 ± 2) × 1011 eV/cm2 when fired at 620°C and 900°C, respectively. The activation energy in an Arrhenius fit of Dit versus the firing temperature is 0.30 ± 0.03 eV. This indicates that thermally induced desorption of hydrogen from SiH bonds at the poly‐Si/SiOx interface is not the root cause of depassivation. Postfiring annealing at 425°C can improve the passivation again. Samples with SiNx capping layers show an increase in J0 up to about 100 fA/cm2 by firing, which can be attributed to blistering and is not reversed by annealing at 425°C. On the other hand, blistering does not occur in poly‐Si samples capped with AlOx layers or AlOx/SiNy stacks, and J0 values of 2–5 fA/cm2 can be achieved after firing. Those findings suggest that a combination of two effects might be the root cause of the increase in J0 and Dit: thermal stress at the SiOz interface during firing and blistering. Blistering is presumed to occur when the hydrogen concentration in the capping layers exceeds a certain level.

In situ Y2O3 on p-In0.53Ga0.47As—Attainment of low interfacial trap density and thermal stability at high temperatures

By in situ depositing Y2O3 on a pristine p-In0.53Ga0.47As surface under ultra-high vacuum, we have attained a low interfacial trap density (Dit) of (2–5) × 1011 eV−1cm−2 from the mid-gap to the valence band edge. The Dit values were extracted from the conductance contours measured from 300 K to 77 K. The small frequency dispersions of 1.2%/dec (300 K) and 0.28%/dec (77 K) in the accumulation region of the capacitance–voltage (CV) characteristics and very small frequency-dependent flatband voltage shifts of 0.021 V/dec (300 K) and 0.011 V/dec (77 K) indicate low border trap densities and low Dit's; these experimental results have not been achieved in previous reports of oxide/p-In0.53Ga0.47As. The Y2O3/p-In0.53Ga0.47As heterostructure also exhibited a high thermal stability of 800 °C, as observed by the low Dit values, small CV frequency dispersions, and an abrupt interface without inter-diffusion in cross-sectional scanning transmission electron microscopy images. Our work has demonstrated a long-sought remedy for the effective passivation of p-type In0.53Ga0.47As, paving the way to high-performance electronic and optoelectronic In0.53Ga0.47As devices.

Mg:TiO2 alloy thin films based MOS capacitors grown on GaAs substrates

Electron beam evaporation technique is employed to synthesise TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 thin films (TFs) grown on (100) n-type GaAs substrates. Field emission gun-scanning electron microscope (FEG-SEM) results show that the TFs have a thickness of ~225 nm. The non- contact atomic force microscopy (NC-AFM) images shows the pore volume of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 TFs enhanced gradually. UV-Vis absorption measurements are performed on the samples to determine the main bandgap and defect level transition of the material. A unique modified Urbach theoretical model has been introduced to simulate the experimental absorption spectrum. The main bandgap energy of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 samples are calculated to be ~3.45 eV, 3.85 eV and 4.30 eV respectively. A gradual enhancement in main bandgap transition probability and decrease in defect level transition of the material has been observed with enhanced incorporation of Mg into the TiO2 host material. X-ray diffraction (XRD) is performed, which shows a continuous change in lattice constant of TiO2 with Mg. Current (I)-voltage (V) characteristics of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 Schottky devices revealed that the leakage current at −1 V was 1.28 × 10−6 A, 1.46 × 10−9 A and 2.44 × 10−10 A respectively. Capacitance (C)–voltage (V) measurements are performed on the devices at different frequencies. A theoretical simulation has been adopted by amending the delta depletion model at 1 MHz. The dielectric constant and the flat band voltage of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 devices are found to be 100, 120 and 160 and 16.1 V, 14.7 V and 9.7 V respectively. Hill-Coleman’s method shows a gradual enhancement of the density of interface states (Dit) with Mg concentration. The calculated Dit value of the TiO2, Mg0.1Ti0.9O2 and Mg0.2Ti0.8O2 TF devices are ~6.16 × 1010 eV−1 cm−2, 6.44 × 1010 eV−1 cm−2 and 1.11 × 1011 eV−1 cm−2 respectively. The observed C-V hysteresis confirms an enhancement in the charge retention into the film with increasing Mg concentration, which in turn improves the memory window (MW) from ~0.36 V (at±7 V) to ~0.67 V (at±7 V) and ~0.87 V (at±10 V) to ~1.0 V (at±10 V) with sweeping voltage.

Interface characteristics of β-Ga2O3/Al2O3/Pt capacitors after postmetallization annealing

Interface characteristics of frequency dispersion, flatband voltage (Vfb) shift, fixed charge (QIL), and interface state density (Dit) in β-Ga2O3/Al2O3/Pt capacitors were investigated after postmetallization annealing (PMA) at 300 °C in N2 using a conductance method and a photo-assisted capacitance-voltage technique. After PMA, no frequency dispersion was observed, and the QIL and Dit values related to interface states near the conduction band edge (Ec) were significantly reduced to the ranges of −4 to +1 × 1011 cm−2 and 3 to 8 × 1011 cm−2 eV−1 at Ec − E = 0.4 eV, respectively, in the capacitors subjected to a low postdeposition annealing (PDA) temperature region of 300–600 °C. In contrast, a large frequency dispersion, and high QIL (−2 × 1012 cm−2), and Dit (4–5 × 1012 cm−2 eV−1 at Ec − E = 0.4 eV) of the capacitors with a high PDA temperature region of 700–900 °C remained. This difference is considered to be due to hard structural changes at the multilayer level by the interdiffusion of Ga and Al at the β-Ga2O3/Al2O3 interface caused by PDA above 700 °C. In contrast, the average Dit values due to the electrons deeply trapped below the midgap between 2.6 and 3.3 eV decreased from 2 × 1012 to 1 × 1011 cm−2 eV−1 as the PDA temperature was increased from 300 to 900 °C, respectively, before PMA. No significant change in Dit below the midgap was observed, regardless of the PDA temperature after PMA. Note that the PMA treatment effectively improved only the interface properties near the Ec after treatment in the low PDA temperature region below 600 °C.

Temperature dependence of interface state density distribution determined from conductance–frequency measurements in Ni/n-GaP/Al diode

The conductance measurements of the non-annealed (D1) and 400 °C annealed (D2) Ni/n-GaP/Al diodes were made over a wide frequency range of (10 kHz to 5 MHz) and temperature of (100–320 K with steps of 20 K) with bias voltage as a parameter. The capacitance and conductance measurement method is one of the most popular non-destructive methods to obtain information about metal–semiconductor (MS) diode interfaces. The interface state density distribution curves were determined over the band-gap energy near the semiconductor energy midgap. The interface state density (Dit) has been seen to be of the order of ∼1012 eV−1 cm−2. The Dit∼T curves have been plotted for different values of bias voltage. The value of Dit increased with increasing measurement temperature, and with increasing voltage from negative bias to positive bias voltage for both diodes. It was seen that the Dit value for D2 diode was greater than that for the D1 diode at each measurement temperature and bias voltage. It was seen in the interface state energy distribution or density distribution curves that the value of Dit has increased from the valence band maximum (Ev) towards conduction band minimum (Ec) at each measurement temperature.