Effect of film stress on different electrical properties of PECVD grown SiNx films and its bilayer structures: A study of Si surface passivation strategy

Abstract

The prevalence of stress during thin film deposition has a substantial influence on the surface passivation of CMOS image sensors (CIS). Our present research thoroughly addresses the effect of film stress on minority carrier lifetime and interface trap density (Dit) of as-deposited and forming gas annealed (FGA, 5% H2, 400 °C for 30 min) SiNx films and their bilayer structures. In this study, plasma-enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD) techniques were utilized to synthesize SiNx and SiNx/(top) Al2O3 bilayer structures. After FGA, the minority carrier lifetime and Dit values for 50 nm-SiNx (1607 μs, 7 × 1011 cm−2eV−1), 30 nm-Al2O3 (2670 μs, 7 × 1011 cm−2eV−1), 7 nm-SiNx/30 nm-Al2O3 (1750 μs, 6 × 1011 cm−2eV−1) and 50 nm-SiNx/30 nm-Al2O3 (2300 μs, 34 × 1011 cm−2eV−1) were found. Our statistical analysis indicates that the stress in the SiNx/Al2O3 bilayer structures introduces defects in the films. This affects the carrier lifetime along with Dit values and hence degrades CIS performance. Further, we also performed a stress simulation of SiNx films which corroborated with the overall analysis. We hope that this work facilitates a better understanding of the stress effect on the surface passivation of CIS applications.