Interface Trap Density Distribution Research Articles

Tuning the Electrical Properties of Tungsten Oxide Thin Films Deposited by Reactive Magnetron Sputtering

Tungsten oxide films are deposited onto glass and silicon substrates using reactive magnetron sputtering. Several studies have revealed difficulties in studying the electrical properties of resistive WOx films. The main objective of this work is to propose the capacitance meter as a method for studying the electrical properties of resistive WOx films. In addition, we aim to establish the correlation between the deposition process and WOx physico-chemical properties. The study of the W-Ar-O2 system hysteresis permitted us to gather the films into four zones, which were delimited by different oxygen flow rate intervals. The identification of these zones was confirmed by the deposition rate, target voltage, chemical composition and electrical properties of the films. A gradual evolution of the capacitance-voltage curves of the metal-oxide-semiconductor structures, with the WOx thin films as the oxide layer, was globally observed with increasing oxygen flow rate. Ion density (Nss) and flat band voltage (Vfb) evolved inversely to oxygen flow rate. The relationship between the evolution of Nss and Vfb and the increase in oxygen flow rate reflects the improvement in oxygen stoichiometry in the WOx films. The WOx-Si interface trap density distribution (Dit) was also studied using the Terman method. It was observed that the films closest to stoichiometry, i.e., WO2 or WO3, showed the lowest values of Dit and Nss.

On Noise Performance of Dual-Gated Silicon FET Biosensors With Schottky Contacts

We analyzed the low-frequency noise (LFN) of dual-gated field-effect transistor (DG-FET) biosensors with Schottky contacts. We found the flicker noise at the sensing insulator-semiconductor interface to be the major noise source while employing Schottky contacts to have minimal noise contribution with a sufficiently large back-gate bias voltage. The measured noise dependence on transconductance further indicated the presence of a nonuniform energy distribution of interface trap density at the said sensing interface. Based on these findings, we argued that the DG structure is advantageous over its single-gated (SG) counterpart; although they possess the same intrinsic lower limit of detection (LLOD), the former could offer a larger signal gain at the optimum LLOD thanks to sufficient channel carrier supply through back-gating instead of biasing the sensing interface toward band edge with higher trap density.

Impact on the Conductance Method of the Asymmetry in the AC Response Induced by Interface Trap Levels

The conductance method has been extensively used to analyze the dielectric-semiconductor interfaces by assuming a continuous density of the interface traps. If dangling bonds are dense at the interface, the wavefunction tails of electrons in the dangling bonds overlap each other to form a continuous density of interface traps. However, as the advanced fabrication process improves the interface quality, the interface traps become dilute. Hence, the density of interface traps may be interpreted as a composition of distinct peaks with less overlapping of trapped electrons, i.e., the discrete localized interface traps. In this regard, we assume that peaks apart from the Fermi level more than the thermal energy affect the conductance method. This is a novel approach to the conventional conductance method. Present model derived in this study is applied on the zirconium oxide—silicon interface fabricated using the atomic layer deposition. As result, we successfully reproduced the asymmetrical conductance in frequency spectrum and obtained the distribution of interface trap density with time constants correspondent to the extracted energy levels. Inclusion of the peak levels shows larger fluctuation in time constants, and the proposed method compensates underestimation in the conventional conductance method.

Determination of bulk and interface density of states in metal oxide semiconductor thin-film transistors by using capacitance–voltage characteristics

A physical-based straightforward extraction technique for interface and bulk density of states in metal oxide semiconductor thin film transistors (TFTs) is proposed by using the capacitance–voltage ( C – V ) characteristics. The interface trap density distribution with energy has been extracted from the analysis of capacitance–voltage characteristics. Using the obtained interface state distribution, the bulk trap density has been determined. With this method, for the interface trap density, it is found that deep state density nearing the mid-gap is approximately constant and tail states density increases exponentially with energy; for the bulk trap density, it is a superposition of exponential deep states and exponential tail states. The validity of the extraction is verified by comparisons with the measured current–voltage ( I – V ) characteristics and the simulation results by the technology computer-aided design (TCAD) model. This extraction method uses non-numerical iteration which is simple, fast and accurate. Therefore, it is very useful for TFT device characterization.

3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향

This paper introduces about the effect on characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom layer and both the bottom and top layer were relatively more affected by heat than the top layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The variation considering the interface trap charge distribution changes less than that excluding it.

Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (Nit) and bulk trapped charge density (Not) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with Nit and Not profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters Nit and Not. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and Nit and Not profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.

Capacitive coupling model and extraction of the molecular interface states in porphyrin-silicon nanowire hybrid field-effect transistor

We modeled and extracted the distribution of interface trap density by grafted molecules on the surface of a silicon nanowire field-effect transistor (SNWFET). The subthreshold current model was employed, and the capacitive coupling model of ideality factor was simplified, using a fully depleted SNWFET. We applied the analytical model to p-channel SNWFET with porphyrin, and extracted the distribution of the molecular interface states. There were 748 and 474 traps (average value) in length (L) = 300 nm and L = 500 nm devices, respectively. The trap energy was in the range of 0.27–0.35 eV.

The Effect of Trapped Charge on Silicon Nanowire Pseudo-MOSFETs

The effects of organic molecules grafted on top of silicon nanowires are modeled as the oxide trap charges (Qot) and interface trap charges (Qit). The device investigated here is a pseudo-MOSFET with a thick bottom oxide (200 nm) and only a thin native oxide (5 nm) on top. With Qot = -5.0 x 10(11) cm(-2) and the U-shaped distribution of interface trap density (Dit) as a function of trap energy (Et), the structures are reproduced through the conventional technology computer aided design (TCAD) simulation tool, and the channel is imaginarily divided into several sections (5 x 5 regions) to apply the localized traps. The electrical parameters are extracted from the each part to quantitatively compare their effectiveness. The local position of the grafted molecules, modeled by these charges, is shown to result in strong variations in the relative change in the threshold voltage and subthreshold swing. These variations are explained by the surface depletion and scattering near the edges of the etched device and the series resistance effect.

Bulk and interface trapping in the gate dielectric of GaN based metal-oxide-semiconductor high-electron-mobility transistors

The trapping phenomena in GaN metal-oxide-semiconductor high-electron mobility transistor structures with 10 and 20-nm thick Al2O3 gate dielectric grown by metal-organic chemical vapor deposition were deeply investigated using comprehensive capacitance-voltage measurements. By controlling the interface traps population, substantial electron trapping in the dielectric bulk was identified. Separation between the trapping process and the interface traps emission allowed us to determine distribution of interface trap density in a wide energy range. Temperature dependence of the trapping process indicates thermionic field emission of electrons from the gate into traps with a sheet density of ∼1013 cm−2, located a few nm below the gate.

Electrical properties of atomic layer deposited Al2O3 with anneal temperature for surface passivation

The electrical characteristics of Al2O3 layers prepared by the atomic layer deposition technique using O3, H2O, and plasma O2, as oxidants are investigated through capacitance–voltage measurements of metal–insulator–semiconductor capacitors. Particular emphasis is placed on the properties of thermal annealed Al2O3 for surface passivation. Capacitance measurements at flatband voltage before and after the application of constant voltage stress in the inversion regime indicate that the charge trapping and hysteresis behavior of the capacitors are more dominant at low temperature annealing. Positive flatband voltage shifts due to negative charge tunneling are also observed under both negative and positive bias voltage polarities. The interface trap densities of O3 and plasma O2-based Al2O3 samples at 450°C decrease by an order of magnitude with increasing annealing temperature, approaching the interface trap density levels in the 1011eV−1cm−2 range. However, H2O-based Al2O3 doesn't change considerably. The interface trap density distribution shows that H2O-based Al2O3/Si annealed over 400°C has depassivated defects, similar to those observed in SiO2/Si interfaces. A comparison of the emitter saturation current density and the interface defect density shows that the interface density at the midgap is not so useful in predicting interface recombination after corona charging.

Frequency dispersion effect and parameters extraction method for novel HfO2 as gate dielectric

The electric characteristic of MOS capacitor with HfO2/SiO2/p-Si grown by ALCVD (atom layer chemical vapor deposition) is investigated. The C-V curves show that the accumulation capacitances take on the frequency dispersion at high frequency. For MOS capacitor with ultra thin HfO2/SiO2 gate stack, different fabrication processes and measurement equipment will cause parasitic effect. Here an equivalent circuit model that can eliminate the frequency dispersion effect is proposed. The C-V characteristics curve at high frequency shows some distortion because of the bulk defects and the interface states. This paper discusses the distortion of the high frequency MOS C-V characteristic curve. A data processing method is advanced and interface trap density distribution in the band gap is presented. By comparing the ideal C-V curve with the experimental C-V curve, the typical electrical parameters of MOS capacitor are extracted, including the shift of flat-band voltage, the oxide charges and the density of interface traps at the SiO2/Si interface.

Sub-bandgap optical subthreshold current spectroscopy for extracting energy distribution of interface states in nitride-based charge trap flash memories

Abstract A sub-bandgap optical subthreshold current spectroscopy (OSCS) is proposed for extracting the energy distribution of interface trap density (Dit) in nitride-based charge trap flash (CTF) memory devices. It is based on the optical response of the subthreshold slope under sub-bandgap photonic excitation. By using the OSCS technique, we comparatively investigated the dominant energy range of the program/erase (P/E) cycling-induced Dit and observed that it is shallow in NROM-type operation and deep in NAND-type operation. Because no electrical pulse is required during extraction and the current is measured not from the substrate contact but from the drain contact, the OSCS technique is expected to be more useful for emerging nano-scale devices in comparison with the conventional charge pumping technique.

Interfacial and Electrical Characterization in Metal–Oxide–Semiconductor Field-Effect Transistors with CeO2 Gate Dielectric

Metal–oxide–semiconductor capacitors (MOSCs) and MOS field-effect transistors (MOSFETs) incorporating cerium dioxide (CeO2) dielectrics were fabricated and investigated. In this work, the electrical and interfacial properties were characterized by capacitance–voltage (C–V) and current–voltage (I–V) measurements. The density of interface trap per unit area (Nit), the density of interface trap per unit area and energy (Dit), the energy distribution of interface trap density, and the effective capture cross section (σs) were studied in details. Experimental results showed that the Nit, Dit, and σs were about 3.4×1010 cm-2, 7.3×1010 cm-2 eV-1, and 9.0×10-15 cm2, respectively. In addition, a comparison of interfacial properties among several gate dielectrics was made.

Asymmetric Energy Distribution of Interface Traps in Germanium MOSFETs with HfO2 Gate Dielectric

In this work, a simple model, with a higher interface trap density in the upper half of Ge bandgap than that in the lower half, is proposed to explain the abnormal behaviors in Capacitance-Voltage characteristics of both p- and n-MOS capacitors on Ge substrate using different surface passivation. Variable rise/fall-time charging pumping measurement is used to study the energy distribution of interface trap density in HfO2 gated Ge MOSFETs. Our results reveal that Dit is higher in the upper half of the Ge bandgap than that in the lower half of the bandgap. These results are also consistent with the observation that n-channel mobility is more severely degraded compared to p-channel for Ge MOSFET.

Energy distribution of interface traps in germanium metal-oxide-semiconductor field effect transistors with HfO2 gate dielectric and its impact on mobility

The energy distribution of interface trap density (Dit) in HfO2 gated germanium metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated by using charge pumping method with variable rise/fall-time measurement. Our results reveal that a high density of interface traps is present in the upper half of the Ge bandgap. As a result, the inversion-layer electron mobility of Ge n-channel MOSFETs was significantly degraded by the Coulomb scatterings. These results are also consistent with the abnormal capacitance-voltage (C-V) characteristics of Ge MOS capacitors.

Spatial distribution of interface trap density in strained channel transistors using the spread of the differential capacitance characteristics in scanning capacitance microscopy measurements

In this letter, the authors obtain, with nanometer spatial resolution, the local spatial distribution of interface trap density (Dit) at the gate oxide-substrate interface across the channel region of a transistor with silicon germanium source/drain (S/D) stressors. The Dit values were extracted using a theoretical model which is based on the correlation of Dit with the change in the full width at half maximum of the scanning capacitance microscopy differential capacitance characteristics. Results show that Dit increases with spatial location, measured from the center of the channel, towards the S/D regions of the strained channel transistor. The large value of Dit near the S/D regions is possibly due to germanium diffusion into the channel region and other resulting structural defects.

Nanoscale germanium MOS Dielectrics-part I: germanium oxynitrides

In this paper, nanoscale germanium (Ge) oxynitride dielectrics are investigated for Ge MOS device applications. The synthesizing methodology and physical properties of these oxynitride films have been examined first. Basic electrical characteristics have been acquired on metal-gated MOS capacitors with Ge oxynitride dielectric on substrates with different dopant types and crystal orientations. Using an optimized oxidation and nitridation recipe, high-quality Ge MOS capacitors with a minimal frequency dispersion and capacitance-voltage hysteresis have been demonstrated. In addition, the Ge oxynitride dielectric-substrate interface has also been analyzed with the combined low-frequency-high-frequency capacitance method that revealed a substantial reduction of interface trap density after the forming gas anneal. An asymmetric interface trap density distribution within the Ge bandgap has been mapped out, which might explain the inferior n-channel Ge MOSFETs with oxynitride dielectric. An abnormality in the general gate leakage behavior has been observed and found to originate from a transient charge-trapping effect.

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.

Electrical Characterization of Germanium Oxide/Germanium Interface Prepared by Electron-Cyclotron-Resonance Plasma Irradiation

We have found excellent electrical characteristics in germanium oxide grown by plasma oxidation for germanium metal-insulator-semiconductor gate dielectric applications. An oxygen plasma stream generated by electron cyclotron resonance was used to oxidize a germanium surface without substrate heating. A transmission electron microscope observation revealed that the obtained germanium oxide/germanium interface is atomically smooth. The energy distribution of interface trap density (Dit) in the upper half of the p-type germanium band gap was measured by the ac conductance method. It is shown that the Dit at the midgap is ∼6 ×1010 cm-2·eV-1 and increases exponentially as the energy increases to the conduction-band edge.

Spatial Distribution of Interface Traps in DeMOS Transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.