Clock Distribution Research Articles

Study of Delay Instabilities in Xilinx FPGA-Embedded Multigigabit Transceivers for Clock Distribution and Synchronization

Study of Delay Instabilities in Xilinx FPGA-Embedded Multigigabit Transceivers for Clock Distribution and Synchronization

The KM3NeT Broadcast optical system network

The optical data transport system of the KM3NeT neutrino telescope at the bottom of the Mediterranean Sea will serve more than 6000 optical modules in the detector arrays with a point-to-point optical connection to the control stations onshore. The ARCA and ORCA detectors of KM3NeT are being installed at a depth of about 3500 m and 2500 m, respectively and their distance to the control stations is about 100 km and 40 km. The two detectors are optimised for the detection of cosmic neutrinos with energies above about 1 TeV (ARCA) and of atmospheric neutrinos with energies in the range 1 GeV– 1 TeV (ORCA). The expected maximum data rate is 200 Mbps per optical module. The implemented optical data transport system matches the layouts of the networks of electro-optical cables and junction boxes in the deep sea. For efficient use of the fibres in the system the technology of Dense Wavelength Division Multiplexing is applied. To comply with the scientific goals of KM3NeT, a time calibration of 1 ns between the many optical modules in the detector arrays is essential for the reconstruction of the neutrino events. For the first time in a deep sea neutrino telescope the White Rabbit protocol over Ethernet is used for the clock distribution. Downstream slow control and base module signals are broadcasted to all optical modules in the detector array. Synchronisation is achieved by communication between a White Rabbit master onshore and a White Rabbit slave unit inside the optical modules. In this contribution the KM3NeT broadcast optical data transport system is presented.

Uncertainty quantification in epigenetic clocks via conformalized quantile regression.

DNA methylation (DNAm) is a chemical modification of DNA that can be influenced by various factors, including age, environment, and lifestyle. An epigenetic clock is a predictive tool that measures biological age based on DNAm levels. It can provide insights into an individual's biological age, which may differ from their chronological age. This difference, known as the epigenetic age acceleration, may indicate the state of one's health and risk for age-related diseases. Moreover, epigenetic clocks are used in studies of aging to assess the effectiveness of anti-aging interventions and to understand the underlying mechanisms of aging and disease. Various epigenetic clocks have been developed using samples from different populations, tissues, and cell types, typically by training high-dimensional linear regression models with an elastic net penalty. While these models can predict mean biological age with high precision, there is a lack of uncertainty quantification which is important for interpreting the precision of age estimations and for clinical decision-making. To understand the distribution of a biological age clock beyond its mean, we propose a general pipeline for training epigenetic clocks, based on an integration of high-dimensional quantile regression and conformal prediction, to effectively reveal population heterogeneity and construct prediction intervals. Our approach produces adaptive prediction intervals not only achieving nominal coverage but also accounting for the inherent variability across individuals. By using the data collected from 728 blood samples in 11 DNAm datasets from children, we find that our quantile regression-based prediction intervals are narrower than those derived from conventional mean regression-based epigenetic clocks. This observation demonstrates an improved statistical efficiency over the existing pipeline for training epigenetic clocks. In addition, the resulting intervals have a synchronized varying pattern to age acceleration, effectively revealing cellular evolutionary heterogeneity in age patterns in different developmental stages during individual childhoods and adolescent cohort. Our findings suggest that conformalized high-dimensional quantile regression can produce valid prediction intervals and uncover underlying population heterogeneity. Although our methodology focuses on the distribution of aging in children, it is applicable to a broader range of populations to improve understanding of epigenetic age beyond the mean. This inference-based toolbox could provide valuable insights for future applications of epigenetic interventions for age-related diseases.

Full-Scale Readout Electronics for the ECHo Experiment

Recent advances in the development of cryogenic particle detectors such as magnetic microcalorimeters allow the fabrication of sensor arrays with an increasing number of pixels. Since these detectors must be operated at the lowest temperatures, the readout of large detector arrays is still quite challenging. This is especially true for the ECHo experiment, which presently aims to simultaneously run 6,000 two pixel detectors to investigate the electron neutrino mass. For this reason, we developed a readout system based on a microwave SQUID multiplexer (μ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mu$$\\end{document}MUX) that is operated by a custom software-defined radio (SDR) at room-temperature. The SDR readout electronics consist of three distinct hardware units: a data processing board with a Xilinx ZynqUS+ MPSoC; a converter board that features DACs, ADCs, and a coherent clock distribution network; and a radio frequency front-end board to translate the signals between the baseband and the microwave domains. Here, we describe the characteristics of the full-scale SDR system. First, the generated frequency comb for driving the μ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mu$$\\end{document}MUX was evaluated. Subsequently, by operating the SDR in direct loopback, the crosstalk of the individual channels after frequency demultiplexing was investigated. Finally, the system was used with a 16-channel μ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\mu$$\\end{document}MUX to evaluate the linearity of the SDR, and the noise contributed to the overall readout setup.

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

Time error accumulation in a hierarchical time and clock distribution network with deterministic optical links

Accurate clock and time distribution is a key requirement for self-triggered streaming data acquisition in the CBM experiment. This distribution is handled by the Timing and Fast Control (TFC) system by clock forwarding and broadcasting the common time over latency-deterministic optical links in a hierarchical FPGA network. The point-to-point optical connections are served by the latency-optimized GBT-FPGA core, which has been developed at CERN. In the presented work, the performance of GBT-FPGA links for time and clock distribution in a scaled TFC system with multiple hops and endpoints has been investigated.

A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators

This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8.9-GHz output. By using the retiming and separate division techniques, frequency coupling is solved, and the implementation of the clock distribution is separated from its noise considerations, which alleviates design complexity. Fabricated in 65-nm CMOS process, the proposed CPPLL is verified, and it achieves −109.9-dBc/Hz@1 MHz phase noise and −71.6-dBc reference spur at 16-GHz output. The integrated jitter is 144 fs from 10 kHz to 100 MHz.

Design of a high-precision clock distribution and synchronization system

In large-scale nuclear and particle physics experiments, there is a high demand for high precision clock distribution and synchronization. In this paper, the design and testing of a high precision clock distribution and synchronization system for the CSR External Target Experiment (CEE) is presented. To achieve high synchronization precision, a dedicated high-quality clock distribution network is designed, while the timestamp synchronization is achieved over the existing trigger link in CEE with a customized protocol in order to simplify the system structure. Automatic metastability elimination and real-time monitoring of both the timestamps on the front end nodes and the clock electronics status are also implemented. The test results indicate that the period jitter of the clock network is better than 4 ps rms, and all the expected functionalities have been achieved successfully.

Synchronization in PLL Networks: Numerical Simulations Using Julia

Clock distribution systems are used in many applications requiring accurate time basis: integrated circuits, computer networks, satellite communications, and Global Position System (GPS). Trying to automatize the design of clock distribution systems, this work presents a general formulation considering the possible topologies and parameters, building a computational tool allowing to design and evaluate the performance of any case to be studied. The developed tool enables to simulate networks setting the number of nodes, internal node parameters, topology, perturbations, and signal propagation delays. The simulation results include response times, synchronization quality, and stability for all types of arrangements: mutually connected, chains, rings, stars, and mixed architectures.

Clock synchronizing radio access networks to picosecond precision using optical clock distribution and clock phase caching

Performing positioning of future mobile devices using trilateration through radio access networks would provide a robust alternative to currently used global navigation satellite systems. However, the positioning accuracy is strongly dependent on the time synchronization accuracy of the antennas used as location reference points. Consequently, achieving sub-30 cm positioning accuracies requires the synchronization of radio access network antennas to sub-nanosecond accuracy. Here we show a clock phase synchronization and optical clock signal distribution approach to clock synchronization in radio access networks that achieves 0.98-ps root-mean-square precision clock synchronization, in a real-time field-trial demonstration on 37.6-km dark fiber, with optical clock frequency synchronization and clock phase caching operating using 25.6-Gb/s commercial transceivers. We quantify the clock synchronization performance of our approach using standard metrics, including time deviation (TDEV) and mean time interval error (MTIE). Furthermore, we estimate the impact of varying the phase update rate used in clock phase caching on the clock synchronization performance of our approach. Through our two combined approaches, we explore a route towards achieving sub-nanosecond clock synchronization in radio access networks.

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area- and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2x2 routers and 4x4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5x for long packets.

Picosecond Synchronization System for the Distribution of Photon Pairs Through a Fiber Link Between Fermilab and Argonne National Laboratories

We demonstrate a three-node quantum network for C-band photon pairs using 2 pairs of 59 km of deployed fiber between Fermi and Argonne National Laboratories. The C-band pairs are directed to nodes using a standard telecommunication switch and the detection system is synchronized to picosecond-scale timing resolution using a coexisting O- or L-band optical clock distribution system.We measure a reduction of coincidence-to-accidental ratio (CAR) of the C-band pairs from 51 ± 2 to 5.3 ± 0.4 due to Raman scattering of the O-band clock pulses. Despite this reduction, the CAR is nevertheless suitable for quantum networks.

Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits

A technology mapping method for reducing the logic stages of RSFQ logic circuits is proposed. Technology mapping, which generates netlists for a target technology from a device-independent form, is the final step in logic synthesis. This method introduces clockless logic gates working without clock pulses into the resultant netlists during technology mapping to reduce the number of logic stages. The reduction of logic stages leads to a reduction of latency in clock cycles and circuit size of clock distribution. The introduction of clockless gates is accomplished using a special supergate library used in technology mapping. The design method of a special library containing supergates, including clockless gates, is shown. A modification to reduce the delay caused by clockless gates is also presented. The proposed method is implemented and evaluated using academic design tool ABC. The evaluation results show a reduction of over 30% in the logic stages and a reduction of over 20% in the number of clocked gates, including D flip-flops for path balancing.

Modal analysis under jittering and kernel clock distribution: single-output identification

Smartphones have attracted attention in the structural health monitoring community due to their embedded multisensory platforms suitable for crowdsourcing innovation. Despite their advantages, smartphone sensors are originally designed for user utility rather than technical engineering applications (e.g. vibration analysis and modal identification). Sampling jitter is among those problems adversely influencing smartphone performance as a scientific device that can be used for characterising civil infrastructure dynamic characteristics. With inconsistencies in the sampling period due to jitter effects, the identified modal frequencies of a structure can deviate from the actual value, which is artificially introduced by smartphone clock errors. In this study, the authors formulate the statistical characteristics of the smartphone sampling period through kernel distribution and apply a digital reconstruction remedy to the sampling jitter problem. Through introductory simulations of a sine wave and physical implementations through shaking table tests equipped with smartphones, the efficiency of kernel distribution diagnosis and the signal-reconstruction remedy is presented. Following the simulation and laboratory applications, the proposed techniques are applied to vibration monitoring of a steel pedestrian bridge in terms of the auto power spectral density and short-time Fourier transform of single-output signals. The results show successful rehabilitation of accelerometer data from smartphones, removing jitter-induced errors to a significant extent and accordingly improving the identification accuracy currently in a single-output setting.

50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution

We demonstrate the functioning of a highthroughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependency between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the pre-designed circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floatingpoint adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Advanced Process 2. We verified the highspeed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

The Real-Time System for Distribution of Clock, Control and Monitoring Commands With Fixed Latency of the LHCb Experiment at CERN

The Large Hadron Collider beauty (LHCb) experiment has gone through a major upgrade for LHC Run 3 at European Organization for Nuclear Research (CERN), scheduled to start in the middle of 2022. The entire readout system of the experiment has been replaced by front-end and back-end electronics that are able to record LHC events at the full LHC bunch crossing rate of 40 MHz. To maintain synchronicity across the full system, clock and control commands are originated from a single readout supervisor (SODIN) and distributed downstream through a passive optical network (PON) infrastructure, reaching all the back-end cards of the readout system, via a two-level hierarchy and using PON splitters. A field programmable gate arrays (FPGA) firmware core, called LHCb-PON and based on the CERN timing, trigger, and control (TTC)-PON, is instantiated on SODIN and all back-end cards and provides the communication protocol while ensuring a stable distribution of control commands within the readout period of 25 ns and a clock signal with fixed and deterministic latency with a precision of a few hundreds of picoseconds. This is achieved by the firmware backbone that provides clock recovery and ensures the transmission of a control word downstream with fixed latency. In addition, the LHCb-PON also provides monitoring functionalities over the upstream link, with less strict timing requirements, connecting multiple back-end cards to the central SODIN. This is achieved by having each back-end card send data upstream through a time-division multiplexing (TDM) scheme. This article describes the implementation, measurements, and results from the usage of the system during the startup of the LHC Run 3.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

Ultrawideband RF-IQ Modulator Using Segmented Nonlinearly Scaled RF-DACs and Nonoverlapping LO Signals

A wideband Cartesian in-phase and quadrature (I/Q) modulator based on dual 10 b RF-digital-to-analog converters (DACs) is presented. Nonoverlapping local oscillator (LO) signals and a segmented nonlinear scaling with scaled unit cells contribute to a high linearity and allow for a low-complexity digital predistortion (DPD). Unit-cell flip-flops (FFs) and a balanced clock distribution enable a high sample rate with little skew. Out-of-band emissions are reduced through drive-slope control of the data-switch inputs. The modulator, implemented in the 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS, operates between 20 and 26 GHz with a peak sample rate of 11 GS/s. It has been used to demonstrate the transmission of a 64-quadrature amplitude modulation (QAM) single-carrier (SC) signal at 13.2 Gb/s, a 256-QAM SC signal at 7.33 Gb/s, and an orthogonal frequency division multiplexing (OFDM) signal comprising four aggregated 400-MHz 64-QAM channels with an error vector magnitude (EVM) of 6.43%. These results demonstrate the potential of the proposed modulator for the realization of ultrawideband transmitters in high-performance millimeter-wave (mmW) systems.

Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses

A clock distribution network (CDN) is a ubiquitous on-chip element that provides synchronized clock signals to all different circuit blocks in the chip. To maximize the chip performance, today’s CDN demands lower jitter, skew, and heat dissipation. Conventionally, on-chip clock signals have been distributed in the electric voltage domain, resulting in increased jitter, skew, and heat dissipation due to clock drivers. While low-jitter optical pulses have been locally injected in the chip, research on effective distribution of such high-quality clock signals has been relatively sparse. Here, we demonstrate femtosecond-precision distribution of electronic clocks using driver-less CDNs injected by photocurrent pulses extracted from an optical frequency comb source. Femtosecond-level on-chip jitter and skew can be achieved for gigahertz-rate clocking of CMOS chips by combining ultralow comb-jitter, multiple driver-less metal-meshes, and active skew control. This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.