Distributed Amplifier Research Articles

Static and dynamic mode evolution in high-power distributed side-coupled cladding-pumped fiber amplifiers

AbstractWe present a theoretical study of mode evolution in high-power distributed side-coupled cladding-pumped (DSCCP) fiber amplifiers. A semi-analytical model taking the side-pumping schemes, transverse mode competition, and stimulated thermal Rayleigh scattering into consideration has been built, which can model the static and dynamic mode evolution in high-power DSCCP fiber amplifiers. The mode evolution behavior has been investigated with variation of the fiber amplifier parameters, such as the pump power distribution, the length of the DSCCP fiber, the averaged coupling coefficient, the number of the pump cores and the arrangement of the pump cores. Interestingly, it revealed that static mode evolution induced by transverse mode competition is different from the dynamic evolution induced by stimulated thermal Rayleigh scattering. This shows that the high-order mode experiences a slightly higher gain in DSCCP fiber amplifiers, but the mode instability thresholds for DSCCP fiber amplifiers are higher than those for their end-coupled counterparts. By increasing the pump core number and reducing the averaged coupling coefficient, the mode instability threshold can be increased, which indicates that DSCCP fibers can provide additional mitigation strategies of dynamic mode instability.

A 3.7–43.7-GHz Low-Power Consumption Variable Gain Distributed Amplifier in 90-nm CMOS

A variable gain distributed amplifier (VGDA) for the Rx path of ultrawideband phased-array system is implemented in 90-nm CMOS process and presented in this letter. In order to achieve high gain and wideband with relative low dc power dissipation (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ), the combination of the conventional distributed amplifier (CDA) and the cascaded single-stage distributed amplifier (CSSDA) is utilized to the circuit. Moreover, the active variable termination resistor (AVTR) is adopted to adjust the flatness of gain. According to the experimental results, the proposed VGDA achieves a 21-dB peak gain with a 40-GHz 3-dB bandwidth (3.7-43.7 GHz), 18-dB gain control range (GCR), and 16° maximum phase variation.

A State-of-the Art Review on Distributed Amplifiers

Distributed amplifiers (DAs) are always considered the best choice for wideband amplification as they offer appropriate gain, matching and noise figure over the large bandwidth. With the recent advancements in microwave integrated circuits, monolithic microwave integrated circuits and device processing technology, DAs have discovered new applications of the wideband amplifier. At mm-wave frequencies, the wideband amplifier is used for several applications such as radar imaging, space radiometry, optoelectronics, high-frequency transceivers, plasma diagnostics, ultra-fast measurement systems and defence systems. The main requirement of these applications is to amplify short pulses or to realize a high data rate. Studies show that DA may also be used for next-generation 100+ Giga-baud/s coherent linear fiber optic applications. This paper presents an overview of various types of DAs. In the paper, the different technologies and design methods used for designing various types of DA (from 2009 to 2019) are reported. Furthermore, a comparative analysis of the gain-bandwidth product based on different technologies is given.

Design and Electromigration Study for a Stacked Distributed Power Amplifier

In this paper, the implementation and electro-migration (EM) study in GaAs pHEMT stacked distributed power amplifier (SDPA) is presented. A 0.2[Formula: see text]7 GHz PA is designed using a 0.15[Formula: see text][Formula: see text]m GaAs pHEMT process, which employs 4-distributed 2-stacked-field effect transistors (FETs) to obtain about 1-watt output power with corresponding power added efficiency (PAE) of 26–32% within a very small chip size of 2.9[Formula: see text]mm2. Using the finite element analysis (FEA), the EM prediction for an SDPA is achieved effectively to find the weakest spot for the stacked distributed PA. This can provide valuable guidance for circuit design and analysis.

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S21), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S11 and S22 are less than −10 dB. The input compression point (P1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm2.

Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI

A pseudo-differential distributed power amplifier (DPA) based on complementary gain stages is presented for wideband femtocell 5G indoor communications in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. Capacitive equalization is used to achieve flat bandwidth over the desired frequency range. Due to the complementary gain stages, no expensive bias-Ts are required. In order to improve reverse isolation and increase the output power, stacking is utilized. The design uses back-biasing to set the drain voltages of the DPA instead of the sensitive gate biases. The differences in the design process between a distributed amplifier (DA) and a DPA are presented. Tradeoffs between gain–bandwidth (GBW), reliability, peak power-added efficiency (PAE), output power, and amplitude-to-phase (AMPM) linearity are explored. The DPA achieves an 11.6-dB gain, a 0.4–31.6 GHz 3-dB small-signal bandwidth, and a 16.4 dBm peak-saturated output power ( $P_{\text {SAT}}$ ) with a 17.2% PAE from the 2.5-V supply. AMPM distortion at output-referred 1-dB compression point (OP 1 dB) and at $P_{\text {SAT}}$ is less than 2°/5° up to the 31 GHz, respectively. It achieves 10 dBm average output power reaching 80/96 gigabit per second (Gbit/s) at 17 GHz with 16/64 QAM modulation. At 28 GHz, it achieves 6.4/4.5 dBm output power with 12/8-Gbit/s data rate with 64/256 QAM modulation.

Synthetic Transmission Lines in Cutoff Operation for Wideband High-Impedance DC Supplies

This brief describes a novel technique for the distribution of dc power based on synthetic transmission lines with a low cutoff frequency. Since after the cutoff the impedance of these lines approaches that of an open, these components are well suited to feed dc power in circuit nodes where high impedance values are required. Narrowband bias networks based on inductors or lambda-quarter (λ/4) stubs can be substituted by the presented wideband design solution. To experimentally validate the approach, two prototypes have been implemented in a 130 nm SiGe technology. The first prototype is a synthetic line with a cutoff frequency of 12 GHz, while the second design is a distributed amplifier (DA) where a synthetic line in cutoff feeds the voltage supply. Compared to traditional approaches based on inductors or λ/4 stubs, the presented technique improves the DA bandwidth by 50% and the flatness of the frequency response. Compared to biasing achieved via the DA termination resistor, the power-added-efficiency (PAE) is doubled. To the best knowledge of the authors, this is a novel general technique for feeding dc power to any circuit from a wideband high-impedance.

A Wideband Gain-Enhancement Technique for Distributed Amplifiers

In this article, a new bandpass distributed amplifier (DA) using a wideband gain-boosting technique is presented. In particular, a feedback network, including a series inductor and a shunt capacitor, is used to generate two peaks at the lower and upper cutoff frequencies of the amplifier's bandpass response. This technique provides a gain enhancement over a wide bandwidth without sacrificing the upper cutoff frequency. A detailed analysis of the two frequencies peaking effect is carried out to support the theory. To verify the concept, a conventional and a gain-enhanced DA are fabricated in an indium-phosphide (InP) heterojunction bipolar transistor (HBT) process. The gainenhanced DA exhibits a measured gain of 10.5 dB with a 4-dB gain improvement compared with the conventional one, covering a 3-dB bandwidth from 60 to 145 GHz. The maximum saturated (Psat) is 20.9 dBm at 75 GHz with the measured 1-dB compression power (P1dB) of 18.5 dBm. The dc power consumption is 440 mW, and the chip size is 1.6 mm × 0.6 mm. To the best of our knowledge, the proposed DA achieves the highest gain boosting over a broad bandwidth compared with the published works.

MORPHOLOGICAL ANALYSIS OF MMIC DISTRIBUTED AMPLIFIERS

An effective way to reduce the complexity and cost of designing microwave integrated circuits (IС) is to develop approaches, techniques, algorithms and software modules for the automated synthesis of circuit and topological solutions. In particular, approaches to the structural‑parametric synthesis of microwave devices based on the principles of artificial intelligence and evolutionary computing are promising. The article presents the results of a morphological analysis of microwave distributed amplifiers (DAs). The DAs manufactured using various MMIC processes (GaAs, GaN, InP, Si, SiGe) were analyzed. A MMIC DA morphological set model was created and presented in the article. The model can be used for the technique, algorithm, and software module development for automated structural‑parametric synthesis of MMIC DA schematics according to the set of characteristics requirements.

Analysis and Design of High Gain-Bandwidth CMOS Distributed Amplifier Utilizing a Cascaded Pseudo Differential Distributed Amplifier

Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9[Formula: see text]dB can be achieved for a bandwidth of 50[Formula: see text]GHz in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. In this amplifier, parameters S[Formula: see text], S[Formula: see text] and S[Formula: see text] are [Formula: see text]12, [Formula: see text]10 and [Formula: see text]18 dB, respectively; noise figure is 4.3–5.8[Formula: see text]dB, and [Formula: see text] is +4[Formula: see text]dBm. This amplifier consumes 220[Formula: see text]mW power and has a chip area of 0.58[Formula: see text]mm2.

Cell Weighting and Gate Inductive Peaking Techniques for Wideband Noise Suppression in Distributed Amplifiers

This paper presents a noise suppression method to improve noise figure (NF) performance of a distributed amplifier (DA) in a broad frequency range. In the proposed DA topology, the input matching resistor, which remarkably increases the NF, is replaced by a common-gate (CG) stage. The noise contribution of the CG terminating network is suppressed by employing a cell weighting plan in conjunction with a gate-inductive peaking technique. Analytical methods and a circuit implementation in a $0.18~\mu \text{m}$ CMOS technology verify that the proposed noise suppression technique provides lower NF compared with the conventional DA (CDA) topology in the entire frequency range. This is in contrast to other reported low-noise DA topologies which decrease the noise contribution of the input matching element only in a limited range of frequencies. The measurement results demonstrate an average gain of 9.5 dB in 1-20 GHz frequency range, a noise figure less than 4 dB and 5.8 dB up to 16 GHz and 20 GHz, respectively, and an average IIP3 of 5.3 dBm. The chip occupies an area of 1.2 mm2, including pads, and consumes a current of 24 mA from 1.8 V supply.

A Wideband Highly Linear Distributed Amplifier Using Intermodulation Cancellation Technique for Stacked-HBT Cell

In this article, a wideband linearization technique for distributed amplifiers (DAs) is presented. In particular, an auxiliary transistor is employed to create additional intermodulation distortion components that will be feed-forwarded to the output of each gain unit cell to significantly suppress the third-order intermodulation (IM3) distortion. To verify the concept, two DAs are fabricated in an indium phosphide (InP) process. One amplifier employs a conventional stacked-heterojunction bipolar transistor (HBT) gain unit cell, and the other linearized amplifier utilizes the proposed technique. The linearized DA exhibits a measured gain of 10.5 dB with a 3-dB gain bandwidth from dc to 90 GHz. The maximum 1-dB gain compression output power ( $P_{\text {1 dB}}$ ) is 20.5 dBm, and the third-order intercept point (OIP3) is 33 dBm. Compared to the conventional amplifier, the two values are improved by 3.5 and 4.5 dB on average, respectively. Moreover, the linearization technique only increases very little dc power consumption at high power and has the same chip size as compared to the conventional design. To the best of the authors’ knowledge, compared to published state-of-the-art DAs, the proposed DA achieves among the highest OIP3 over a wide bandwidth.

A Cascaded Multi-Drive Stacked-SOI Distributed Power Amplifier With 23.5 dBm Peak Output Power and Over 4.5-THz GBW

This article presents a cascaded distributed power amplifier (DPA) topology with greater than 4.5-THz gain-bandwidth (GBW) product. The DPA uses stacking with multi-drive inter-stack coupling to compensate for the stacked gain cells and input transmission-line (TL) losses. The techniques improve the gain and output power without compromising the bandwidth (BW). The cascaded DPA employs eight-shaped TLs to allow inter-stack coupling in a compact area and for field confinement. A 33-dB gain, 101.5 GHz BW DPA is realized in the 45-nm RFSOI GlobalFoundries process. The amplifier maintains P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> > 18.7 and 21 dBm, respectively, up to 60 GHz, with over 60 GHz P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> 3-dB BW, while demonstrating >14 dBm of average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> for a 30-Gb/s 64-QAM modulated signal, with an error vector magnitude (EVM) <; 5%. The DPA is also able to provide a 72-Gb/s 64-QAM signal with 13.6 dBm average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> from a 13 GHz carrier frequency. To the best of our knowledge, the cascaded multi-drive DPA achieves the highest reported GBW, continuous-wave (CW) P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> , and average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> for 64-QAM 30-Gb/s modulated signal, in a compact core area compared to published silicon-based DPAs with comparable power levels.

A 120-GHz Bandwidth CMOS Distributed Power Amplifier With Multi-Drive Intra-Stack Coupling

This letter presents a distributed power amplifier (DPA) topology that improves both the power combining efficiency and the operation bandwidth. Multi-drive intra-stack coupling is introduced in the design of the gain cells to break the tradeoff between high output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ) requirement and the achieved bandwidth. The proposed technique also compensates for the input transmission line (TL) loss to accommodate more stages and achieve flat gain and higher P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> . A prototype eightstage, 16-dB gain, 120-GHz bandwidth DPA is fabricated in 45-nm CMOS silicon-on-insulator (SOI) using elevated coplanar waveguide (CPW) TLs with a core area of 0.51 mm2. The amplifier maintains an output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> higher than 18 and 20 dBm, respectively, up to 60 GHz and achieves a peak PAE of 19.7% at 15 GHz. A 64-quadrature-amplitude modulation (QAM) modulated signal with data rate 30 Gb/s (5 GBaud/s) is demonstrated at 55 GHz with a 13.5 dBm average POUT and 6.9% PAE while the error vector magnitude (EVM) is kept below 5%. To the authors' knowledge, the achieved 757-GHz gain-bandwidth product (GBW) is the highest among reported non-cascaded DPAs. The DPA has also the highest continuous-wave (CW) and modulated PAE compared to other reported distributed amplifiers (Das).

Experimental Investigations on TMI and IM-FWM in Distributed Side-Pumped Fiber Amplifier

The inter-modal four-wave mixing (IM-FWM) and transversal mode instabilities (TMI) are experimentally studied in high-power distributed side-pumped fiber amplifiers. To the best of our knowledge, we have made the first demonstration of TMI and IM-FWM which can be suppressed simultaneously by increasing the bending diameter. Besides, the experimental results show that the counter-pumping scheme is beneficial to suppress both of IM-FWM and TMI, when comparing with co-pumping scheme. Furthermore, these two effects cannot be observed when the M2 factor is lower than 1.3, which can give a condition to estimate whether these two effects should be considered or not. The pertinent study can provide some guidance for understanding TMI and IM-FWM in the high-power fiber laser and amplifier.

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS

A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Zehnder modulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference-less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in three segments. A digital-assisted distributed driver (DADD) that replaces the input T-line by segmented 2:1 multiplexers and buffers is, thus, proposed. Precise time gating in each segment allows for velocity match in both the DA and optical DAC, as well as the in-segment pre-emphasis without power-hungry analog delay stages. Measurement results show that the driver and CDR achieve 4-VPP differential swing, 1.19-ps rms jitter, and 1.34-W power consumption at 50 Gb/s. An optical transmitter is demonstrated by wire-bonding the driver to the MZM DAC, achieving 50-Gb/s PAM4 output with 6.35-ps rms jitter and improved linearity.

A High-Performance GaN-Modified Nonuniform Distributed Power Amplifier

This article proposes a modified nonuniform distributed power amplifier (NDPA) design to increase the output power and power-added efficiency (PAE) in wideband. In the proposed NDPA, drain-line impedances are recalculated, including the drain-source capacitances, which cannot be ignored as the transistor size becomes larger at high frequencies. In addition, instead of using a large-sized transistor in the first section of the NDPA, the design proposes a method of halving the characteristic impedance by doubling the phase of the drain line. When compared with the conventional NDPA, the modified NDPA shows the power gain and output power characteristics close to those of the ideal NDPA. To obtain high efficiency in the NDPA, a programmable gate-line termination resistance switching technique (PGT) is proposed. The power gain is increased by using the standing wave generated from the mismatched termination, enhancing the PAE. For design verification, two modified NDPA monolithic microwave integrated circuits (MMICs) were fabricated using a commercial 0.25-μm gallium nitride (GaN) high-electron-mobility transistor (HEMT) process. The two-way power-combined NDPA shows an average output power of 20 W or more and a power density of 1.9 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from 6 to 18 GHz. The NDPA using the proposed PGT accomplishes an average output power of 10 W and an average PAE of 20% or more from 6 to 18 GHz.

A 1–160-GHz InP Distributed Amplifier Using 3-D Interdigital Capacitors

A wideband monolithic microwave/millimeter-wave integrated circuit (MMIC) distributed amplifier (DA) using a 3-D interdigital capacitor at the input of the gain cell is demonstrated in an indium phosphide (InP) heterojunction bipolar transistor (HBT) process. The proposed DA using interdigital capacitors improves the input return loss at high frequencies compared with the one implemented with conventional metal–insulator–metal (MIM) capacitors. The fabricated amplifier achieves a measured average gain of 10.5 dB over a 3-dB bandwidth from 1 to 160 GHz. The maximum measured saturated power ( $P_{\mathrm {sat}}$ ) is 17.8 dBm with the corresponding 1-dB compression power ( $P_{\mathrm {1\,dB}}$ ) of 15 dBm at 55 GHz. The amplifier achieves a minimum $P_{\mathrm {sat}}$ of 14.6 dBm up to 110 GHz.

Performance Analysis of a Low-Noise, Highly Linear Distributed Amplifier in 500-nm InP/InGaAs DHBT Technology

This article is an extension of the previous report on an ultrawideband distributed amplifier (DA) in the InP double heterojunction bipolar transistor (DHBT) technology. With the choice of a tricode unit cell, the Miller capacitance is reduced and a larger bandwidth (BW) is obtained. Measured S-parameters show a 3-dB BW of near dc to >170 GHz with a gain of 12 dB. In addition, the circuit operates in low dc bias conditions, thus yielding a low measured noise figure (NF) of 8 dB over the frequency range of 5–50 GHz and 12 dB at 135 GHz. Within the 5–50-GHz frequency range, the NF is only 0.5 dB higher than the NF of a similar DA with cascode unit cell. When the circuit is measured for large-signal condition, it reaches a 1-dB output compression point, $P_{\mathrm {1\,dB}}$ , of 8.4 dBm at 150 GHz, a saturated output power of approximately 10 dBm, and an associated maximum power-added efficiency (PAE) of 6%. This is the best linearity as well as the highest saturated output power and PAE reported at this frequency for DAs. When measured at 20 GHz, the circuit shows a $P_{\mathrm {1\,dB}}$ , of 9 dBm and output referred third-order intercept point of 22 dBm, a saturated output power of 11 dBm, and an associated maximum PAE of 6%, thereby proving its uniform large-signal character within the full band. In short, this circuit brings in the unique combination of low NF, highly linear characteristics, and high PAE simultaneously together over large BW. Furthermore, the circuit consumes 180 mW of dc power only.

A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells

This article proposes a complementary distributed power amplifier (DPA) using stacked gain cells with multiple input driving signals. The stack multi-drive compensates for the increasing input transmission line (TL) and stack losses as frequency increases and results in bandwidth (BW) extension with a flat gain response. The technique simultaneously increases the gain-BW (GBW) product and the output power at high frequencies while maintaining a smaller chip area compared with the conventional DPA design. A broadband active splitter is introduced before the output stage to create two complementary distributed paths which are exploited for AM–AM and AM–PM non-linearity compensation. The CMOS DPA is implemented in 45-nm RFSOI with a core area of 0.31 mm2. The amplifier has a 23-dB gain and 108-GHz 3-dB BW from true-dc frequency with no need for external bias tees. The DPA maintains a P1 dB and PSAT over 16.9 and 18.4 dBm, respectively, from dc-to-70 GHz, with a 70-GHz PSAT 3-dB BW. When operated with modulated signals, the DPA provides over 100 Gb/s in both 64-QAM and PAM-4 modulations. To the best of our knowledge, the CMOS DPA reports the highest GBW (1.525 THz), the highest data rate in 64-QAM for carriers up to 59 GHz, and the highest single-ended output swing in PAM-4 modulation.