A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS

Abstract

A 50-Gb/s four-level pulse-amplitude modulation (PAM4) silicon photonic transmitter is presented, which is composed of a 40-nm bulk CMOS driver hybrid integrated with a 180-nm silicon-on-insulator (SOI) CMOS Mach–Zehnder modulator (MZM). To recover and demodulate 50-Gb/s PAM4 data into dual-25-Gb/s nonreturn to zero (NRZ) streams for the co-designed MZM digital-analog converter (DAC), a reference-less clock and data recovery (CDR) is integrated, and to achieve high swing and high speed, the driver is made in a distributed amplifier (DA), employing push–pull cells that are grouped in three segments. A digital-assisted distributed driver (DADD) that replaces the input T-line by segmented 2:1 multiplexers and buffers is, thus, proposed. Precise time gating in each segment allows for velocity match in both the DA and optical DAC, as well as the in-segment pre-emphasis without power-hungry analog delay stages. Measurement results show that the driver and CDR achieve 4-VPP differential swing, 1.19-ps rms jitter, and 1.34-W power consumption at 50 Gb/s. An optical transmitter is demonstrated by wire-bonding the driver to the MZM DAC, achieving 50-Gb/s PAM4 output with 6.35-ps rms jitter and improved linearity.