A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

Abstract

The design of a dual-mode, 19-58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5-29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear equalizer (CTLE), a configurable 32-way time-interleaved 3-to-7-bit successive-approximation-register (SAR) analog to digital converter (ADC), a 14-tap feed forward equalizer (FFE)/one-tap decision feedback equalizer (DFE) digital signal processing (DSP), and a baud-rate clock and data recovery (CDR). A four-tap voltage mode transmitter with two pre-cursor taps and one post-cursor tap, incorporates impedance control loop to meet return loss requirements while maintaining good PAM-4 level mismatch ratio of 0.98. At 56 Gb/s, the transceiver achieves the <;1e-12 bit error rate (BER) without explicitly added crosstalk, <;1e-6 BER with 2 mVrms (crest-factor of 10) additional crosstalk, over a 32-dB channel while consuming 9.7 pJ/bit with 7-bit ADC. The transceiver equalizes channel losses up to 46 dB with pre-forward error correction BER <;1e-5 at 58 Gb/s without additional crosstalk. With 3-bit ADC, it achieves 6.4 pJ/bit over a clean 7.4-dB channel.