Distortion Ratio Research Articles

A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.

All-digital calibration algorithm based on channel multiplexing for TI-ADCs

An adaptively calibration structure featured by channel multiplexing that can simultaneously calibrate the offset, gain, and timing mismatch errors existing in TI-ADC (Time-Interleaved ADC) channels in pure digital domain is proposed, which focuses on the problem of limited input signal bandwidth and high calibration hardware overhead. In error compensation aspect, these three mismatch errors are compensated simultaneously by adaptive method. The gain mismatch compensation employed here can help to overcome the deviation that would exist when the first-order Taylor compensation was employed alone for the timing mismatch, which can significantly improve the calibration effect in high-frequency band instead of employing complex high-order Taylor compensation structure. The total calibration algorithm is implemented using FPGA. For the 4-channel, 1 GS/s and 14-bit TI-ADC, the signal-to-noise distortion ratio (SNDR) of the system is increased from 26.19 dB to 84.37 dB, and the spurious free dynamic range (SFDR) is increased from 29.35 dB to 98.49 dB when the input signal normalized frequency f in / f s is 0.975.

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).

A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC

This article reports a fourth-order continuous-time (CT) delta&#x2013;sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain&#x2013;bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor

Beamforming is an essential tool for speaker selection and rejection of environmental noise in automatic speech recognition. This work harnesses the efficiency of delay-and-sum (DAS) beamforming by combining it with constant-directivity beamforming (CDB) and frequency-domain feature extraction. CDB facilitates DAS by restricting the bandwidth for different microphone configurations. An array of sigma-delta modulators (SDMs) digitizes eight microphone inputs. The design takes advantage of bitstream processing of the modulator outputs for beamforming and extracting 60 Mel spectrum power features. The prototype device is fabricated in the 40-nm CMOS and occupies 1.1 mm². Each SDM consumes 91 mW and has a measured signal-to-noise and distortion ratio of 84 dB for an 8-kHz bandwidth. The beamformer and feature extractor consume a dynamic power of 76 and 122 mW, respectively. The entire power consumption of the prototype is 3.95 mW, including leakage power. Processing the Mel spectrum outputs with a DNN, the keyword spotting accuracy in the presence of noise improves from 74% without beamforming to 93% with beamforming.

A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue

Noise-shaping (NS) successive approximation register (SAR) analogue-to-digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications. NS SAR ADCs employing a passive integrator are good candidates for their omission of power-hungry and scaling-unfriendly amplifiers. However, existing passive NS SAR ADCs have a very limited degree of freedom in realising their noise transfer function (NTF), resulting in poor in-band noise suppression. In this letter, a passive switched-capacitor 2nd-order NS SAR ADC that is the first of its kind to offer controllable complex poles to optimise the NTF is proposed. This is achieved by eliminating a capacitor charge clearing operation in a conventional 1st-order NS SAR. The proposed NS SAR ADC also offers simple circuits insensitive to process–voltage–temperature (PVT) variations, and small area with only two extra clock phases. Transistor-level circuit simulation of a 7-bit, 8-MHz bandwidth, 128 MS/s prototype in a 65-nm CMOS shows a 70 dB signal to noise and distortion ratio (SNDR), an improvement of 19 dB compared to that of a regular 7-bit SAR ADC.

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the DA can be hidden behind the comparator latching time. Dedicated latches for each digital-to-analog converter (DAC) element eliminate the need for DAC switching logic. The proposed inverter-inserted three-stage comparator significantly reduces the input-referred offset of the comparator. The prototype 6-bit 700 MS/s SAR ADC was implemented in a 28 nm CMOS process and has a small 0.0012 mm2 area. The measured peak DNL and INL without any mismatch calibration were 0.33 and 0.27 LSB, respectively. With Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 34.07 and 47.52 dB, respectively. The power consumption was 1 mW under a supply voltage of 1.0 V, leading to a Walden figure of merit (FoM) of 34.6 fJ/conversion-step at 700 MS/s.

A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

A 10-bit cyclic ADC with current sub-DAC for column readout of CMOS image sensors (CIS) is presented in this paper. By charging and discharging sampling capacitors with current, reference voltages are static and stable, and thus the proposed cyclic ADC is suitable to be adopted in large-array readout circuit of CIS. The proposed cyclic ADC is designed in 0.11 μm 1-poly 4-metal CMOS technology. Large-array readout circuit of CIS based on the proposed cyclic ADC was simulated. According to the results of simulation, the proposed cyclic ADC under 3.3/1.5 V supply voltages achieves +0.30/-0.50 LSB maximum differential non-linearity (DNL), +0.80/-1.30 LSB maximum integral non-linearity (INL). It shows a 60.6 dB signal-to-noise and distortion ratio (SNDR) at 333 kS/s sample rate. Meanwhile, the proposed cyclic ADC can work stably at different process corners. The root mean square error (RMSE) of the transient positive reference voltage is 28 mV and it's 27 mV of the transient negative reference voltage. The proposed design effectively reduces the reference voltage fluctuation. Compared with the traditional 333 kS/s 10-bit cyclic ADC, the proposed one can reach the same analog to digital conversion accuracy and reduce power dissipation by 16%.

Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems — A Review

In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed.

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

Performance and Optimization of Reconfigurable Intelligent Surface Aided THz Communications

TeraHertz (THz) communications can satisfy the high data rate demand with massive bandwidth. However, severe path attenuation and hardware imperfection greatly alleviate its performance. Therefore, we utilize the reconfigurable intelligent surface (RIS) technology and investigate the RIS-aided THz communications. We first prove that the small-scale amplitude fading of THz signals can be accurately modeled by the fluctuating two-ray distribution based on two THz signal measurement experiments conducted in a variety of different scenarios. To optimize the phase-shifts at the RIS elements, we propose a novel swarm intelligence-based method that does not require full channel estimation. We then derive exact statistical characterizations of end-to-end signal-to-noise plus distortion ratio (SNDR) and signal-to-noise ratio (SNR). Moreover, we present asymptotic analysis to obtain more insights when the SNDR or the number of RIS&#x2019;s elements is high. Finally, we derive analytical expressions for the outage probability and ergodic capacity. The tight upper bounds of ergodic capacity for both ideal and non-ideal radio frequency chains are obtained. It is interesting to find that increasing the number of RIS&#x2019;s elements can significantly improve the THz communications system performance. For example, the ergodic capacity can increase up to 25&#x0025; when the number of elements increases from 40 to 80, which incurs only insignificant costs to the system.

Optimization Algorithms based compensation of mismatches in Time interleaved Analog to Digital Converters

Time interleaved analog to digital converters (TIADCs) play a significant role in signal processing wherever higher sampling rates are required. However, TIADCs suffer from various mismatches like sampling time, dc offset, gain, bandwidth etc. This results in generation of erroneous signal. Numerous methods were proposed for estimation of these mismatches and for correction of the erroneous signal. Optimization algorithms like genetic algorithm (GA), differential evolution (DE) algorithm were also used for estimation of mismatches. An overview of these algorithms and their performance comparison, with respect to various signal quality metrics like signal to noise ratio (SNR), signal to noise, distortion ratio (SNDR) etc, is given in this article.

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

The rapid development of artificial intelligence (AI) and Internet of Things (IoT) increase the requirement for edge computing with low power and relatively high processing speed devices. The computing-in-memory (CIM) schemes based on emerging resistive nonvolatile memory (NVM) show great potential in reducing the power consumption for AI computing. However, the inconsistency of the NVM may significantly degenerate the performance of the neural network. In this article, we propose a low power resistive RAM (RRAM)-based CIM core to not only achieve high computing efficiency but also greatly enhance the robustness by bit line (BL) regulator and BL weight mapping algorithm. The simulation results show that the power consumption of our proposed 8-bit CIM core is only 12.6 mW ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$256\times 256$ </tex-math></inline-formula> at 8b). The spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR) of the CIM core achieve 62.64 and 45.92 dB, respectively. The proposed BL weight mapping scheme improves the top-1 accuracy by 2.46% and 3.47% for AlexNet and VGG16 on ImageNet Large Scale Visual Recognition Competition 2012 (ILSVRC 2012) in 8-bit mode, respectively.

Design of a Barometer-Based Pulse-Taking Device With In Vivo Validation Against High-Frequency Ultrasound Pulse Wave Imaging

Wrist-site pulse-sensing devices have drawn increasing attention for daily monitoring of human body conditions in the context of western medicine and modernization of traditional Chinese medicine (TCM) palpation. Existing tactile pulse sensors are deemed to only access the superficial tissue layer as surface detectors but have not been validated against medical imaging of the radial artery and its pulsation. We hereby proposed to employ high-frequency (15.6MHz) and high frame-rate (1000fps) ultrasound radial pulse wave imaging (US-rPWI) to substantiate human radial pulse-taking. We first presented an easy-to-fabricate, cost-effective pulse-sensing prototype based on a commercial off-the-shelf (COTS) barometer. The prototype performance was evaluated using a homemade pressurized vessel-mimicking phantom and 30 different <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in vitro</i> pulses outputted from a TCM palpation training machine. Phantom experiments evidenced accurate portrayal of dynamic pressure waveforms (mean distortion ratio: 3.38±0.07%, compared with the ground truth). <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In vivo</i> validation on human pre- and post- prandial pulses was further performed. US-rPWI revealed significantly diminished pulse amplitudes and gradual waveform deformation from the arterial wall to the skin layer. Nevertheless, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in vivo</i> pulse waveforms detected at the skin surface by the prototype were highly correlated (correlation coefficient: 0.926±0.07) with those obtained from the radial arterial wall by US-rPWI. Moreover, the changes in post-prandial pulse waveforms detected by both the prototype and US-rPWI were in excellent agreement with those in TCM literature, thus demonstrating the sensitivity of human pulse-taking in quantitative assessment of health conditions at the point of care and providing more clinical evidence for the modernization of TCM sphygmology.

Layered Convolutive Nonnegative Matrix Factorization for Speech Separation

Abstract Nonnegative matrix factorization (NMF) has attracted significant attention for its good performance in single-channel speech separation. The improved algorithms of NMF have become research hotspots. Layered NMF (LNMF), an improved algorithm, can express the source signal more accurately for its multilayer structure. However, LNMF sometimes performs poorly because it ignores the short-term correlation of speech signals. Based on LNMF and the advantages of Convolutive NMF (CNMF), we proposed a Layered Convolutive NMF(LCNMF) algorithm for single-channel speech separation. The LCNMF corporates the multilayer structure into the NMF and expands the convolution of the top-level NMF model. During the training, NMF is used to learn the non-top-level basis matrices, and CNMF is used to learn the top-level basis matrix, then combined with each single-layer of basis matrix. During the prediction, CNMF is used to separate mixed signals. The results on the dataset MIK-1K showed that LCNMF outperformed NMF and LNMF for separating the mixture of single-channel speech signals. LCNMF improved by 0.019, 1.049dB, 1.305dB, and 0.851dB on average compared with NMF, and improved by 0.007, 0.172dB, 0.090dB, and 0.366dB on average compared with LNMF in sort-term objective intelligibility (STOI), Source to Distortion Ratio (SDR), Source to Interference Ratio (SIR) and Source to Artifacts Ratio (SAR)

Blind Speech Separation and Dereverberation using neural beamforming

In this paper, we present the Blind Speech Separation and Dereverberation (BSSD) network, which performs simultaneous speaker separation, dereverberation and speaker identification in a single neural network. Speaker separation is guided by a set of predefined spatial cues. Dereverberation is performed by using neural beamforming, and speaker identification is aided by embedding vectors and triplet mining. We introduce a frequency-domain model which uses complex-valued neural networks, and a time-domain variant which performs beamforming in latent space. Further, we propose a block-online mode to process longer audio recordings, as they occur in meeting scenarios. We evaluate our system in terms of Scale Independent Signal to Distortion Ratio (SI-SDR), Word Error Rate (WER) and Equal Error Rate (EER).

Calibration of Mismatches in Time-Interleaved ADCs Using Teacher Learner-Based Optimization Algorithm

Sampling a signal at elevated sampling rates can be easily achieved by using time-interleaved analog-to-digital converters (TIADCs). TIADCs have more than one ADC in parallel. Each ADC samples the signal with a time gap of one sampling period and hence known as TIADC. The samples from all these ADCs are combined to reconstruct the signal. But the disadvantage of TIADCs is that they have mismatches like sampling time, gain and phase offset. The proposed work focuses on estimation and correction of these mismatches. For estimation of mismatches, teacher learner-based optimization (TLBO) algorithm was used and the estimated mismatches were used for correction by applying suitable operations. The proposed algorithm was applied for four-channel TIADCs. For estimation, a pilot signal is used which in this case is a monotonic sinusoidal signal. The estimation of mismatches was accurate and the correction was implemented for TIADCs with a sinusoidal input signal and the enhancement in signal quality was evaluated by finding signal-to-noise ratio (SNR) and signal-to-noise and distortion ratio (SNDR). There is a significant enhancement in SNR and SNDR. The average enhancements in SNR and SNDR are 50 and 46[Formula: see text]dB, respectively.

Reliability Demodulation Algorithm Design for Phase Generated Carrier Signal

Phase-generated carrier (PGC) demodulation technology has been widely used in fiber-optic interferometric sensors system in recent years. Nonlinear errors caused by interference noise and parasitic amplitude modulation (AM) are key factors that affect the reliability of traditional PGC demodulation system based on arctangent (PGC-Arctan) algorithm. In order to enhance the reliable performance of PGC demodulation system under the conditions of low signal-to-noise ratio (SNR) and high parasitic AM interference, an ellipse fitting algorithm based on the Gauss–Newton iteration (GNI) is proposed, which is called the PGC-Arctan-GNI demodulation algorithm. The proposed algorithm uses the Euclidean distance to accurately estimate the geometric parameters of ellipse, which can correct the nonlinear distortion of the demodulated signal. In addition, the PGC demodulation system designed based on GNI algorithm has the advantages of strong antinoise ability, good antiparasitic AM ability, and widely dynamic range of the input signal amplitude. Experimental results show that, compared with the direct demodulation algorithm and the ellipse fitting algorithm based on the least squares (LS) method, the SINAD value of the proposed algorithm is always greater than 30 dB and higher than the other two algorithms under the condition of low SNR. Under the condition that the parasitic AM index <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> changes from 0 to 0.5, the signal-to-noise and distortion ratio (SINAD) curve of the proposed algorithm is more stable than the curves of the other two algorithms, and the fluctuation range of the SINAD value does not exceed 3 dB. This algorithm also has a wider input signal amplitude range than the LS algorithm. Especially, when the amplitude of the measured signal is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pi$</tex-math></inline-formula> /2, the relative amplitude error of the GNI algorithm is less than 2% and significantly smaller than the LS algorithm. Finally, the demodulation results using real measured data in the actual system show that the frequency and amplitude of the demodulated signal are same as the original signal. At the same time, the SNIAD value of this system reaches 67.40 dB, the spurious-free dynamic range value reaches 68.82 dB, and the total harmonic distortion value reaches -68.40 dB@1 KHz. In summary, the proposed PGC-Arctan-GNI algorithm can eliminate system nonlinear errors caused by the parasitic AM, harmonics, and noise interference by estimating the ellipse parameters, thereby effectively enhancing the stability and reliability of the PGC demodulation system.

A 12-bit, 1.1-GS/s, Low-Power Flash ADC

In this article, an efficient architecture for a low-power, high-resolution flash analog-to-digital converter (flash ADC) is presented. It operates at 12-bit resolution with a sampling frequency of 1.1 GS/s. The architecture is a segmented one consisting of three subflash ADCs that we call SADC1, SADC2, and SADC3. During the operation, SADC1 detects the MSB bit, and SADC2 detects the intermediate bits, while SADC3 detects the finer bits of the flash ADC. Furthermore, SADC1 has a 1-bit resolution, SADC2 has a 6-bit resolution, and SADC3 has a 5-bit resolution. The binary operation related to 12-bit resolution is achieved by combining the subflash ADCs, thermometer digital outputs, and an encoder. The ADC has been fabricated in Global Foundry (GF) 65-nm standard CMOS process. The measured performance parameters show a differential nonlinearity (DNL) of &#x00B1;0.24 LSB, an integral nonlinearity (INL) of &#x00B1;0.45 LSB, a signal-to-noise and distortion ratio (SNDR) of 64.55 dB, a spurious-free dynamic range (SFDR) of 73.9 dB, and an effective number of bits (ENOB) of 10.43 bits. Also, power consumption is found to be 15.10 mW at 1.1-GS/s sampling frequency and 1.2-V supply voltage. The ADC achieves an FOM of 9.95 fJ/conversion-step (c-s) at the Nyquist input frequency and occupies a core area of 0.084 mm².

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.