Discrete Power MOSFET Research Articles

Long-Term Lifetime Prediction of Power MOSFET Devices Based on LSTM and GRU Algorithms

Predicting the long-term lifetime of power MOSFET devices plays a central role in the prevention of unprecedented failures for power MOSFETs used in safety-critical applications. The various traditional model-based approaches and statistical and filtering algorithms for prognostics have limitations in terms of handling the dynamic nature of failure precursor degradation data for these devices. In this paper, a prognostic model based on LSTM and GRU is developed that aims at estimating the long-term lifetime of discrete power MOSFETs using dominant failure precursor degradation data. An accelerated power cycling test has been designed and executed to collect failure precursor data. For this purpose, commercially available power MOSFETs passed through power cycling tests at different temperature swing conditions and potential failure precursor data were collected using an automated curve tracer after certain intervals. The on-state resistance degradation data identified as one of the dominant failure precursors and potential aging precursors has been analyzed using RNN, LSTM, and GRU-based algorithms. The LSTM and GRU models have been found to be superior compared to RNN, with MAPE of 0.9%, 0.78%, and 1.72% for MOSFET 1; 0.90%, 0.66%, and 0.6% for MOSFET 5; and 1.05%, 0.9%, and 0.78%, for MOSFET 9, respectively, predicted at 40,000 cycles. In addition, the robustness of these methods is examined using training data at 24,000 and 54,000 cycles of starting points and is able to predict the long-term lifetime accurately, as evaluated by MAPE, MSE, and RMSE metrics. In general, the prediction results showed that the prognostics algorithms developed were trained to provide effective, accurate, and useful lifetime predictions and were found to address the reliability concerns of power MOSFET devices for practical applications.

Simplified five-level voltage source inverter with level-phase-shifted carriers based modulation technique

<p>A simplified circuit topology of the five-level pulse width modulation (PWM) inverter for DC-AC power conversion with no-isolated DC voltage sources and reduced switching device number is presented in this paper. The inverter circuit is based on the three-level H-bridge inverter configuration. The developed five-level inverter needs only five controlled power switches and four isolated gate drive circuits. Furthermore, the proposed topology does not require bidirectional power semiconductor controlled switches, hence a conventional discrete power MOSFETs or IGBTs can be used to build the inverter circuits. To obtain a better quality output voltage waveform, the level-phase-shifted carriers based sinusoidal pulse width modulation control was applied to produce a five-level PWM voltage waveform. The proposed inverter circuit was examined by using computer simulation with Power PSIM software. The basic principle operation of the inverter circuit was verified experimentally in laboratory using two non-isolated DC voltage sources as the inputs of the inverter’s prototype circuit. Some analysis of inverter’s output waveforms are provided and discussed. <em></em></p>

Remaining Useful Lifetime Estimation for Power MOSFETs Under Thermal Stress With RANSAC Outlier Removal

Reliability of power converters is crucial for mission critical systems. Among the components that are susceptible to failure, power semiconductor devices are one of the major causes of the power converter failures. This paper focuses on the remaining useful lifetime (RUL) estimation of degraded power MOSFETs, which are stressed by thermal cycling. The relative change in on-state resistance is identified as the fault signature. A data-driven RUL estimation algorithm based on a linear approximation model is proposed. The empirical coefficients are estimated by the classical least squares, where the outliers are removed by random sample consensus (RANSAC) algorithm. A sliding window approach is used to track the nonlinearities. The window size, threshold value, and number of samples used by RANSAC are optimized with the genetic algorithm. The accuracy of the proposed RUL estimation tool is verified on a number of thermally aged discrete power MOSFET data.

Remaining Useful Lifetime Estimation for Thermally Stressed Power MOSFETs Based on <sc>on</sc>-State Resistance Variation

The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic check-ups and costly interruptions. Thermal cycling is one of the main techniques to accelerate the package-related failure progress. In this paper, first, a custom designed accelerated aging platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously is introduced. Based on the collected experimental data, the variation of the on -state resistance is identified as the failure precursor, and an exponential degradation model that fits successfully with the experimental data are developed. The remaining useful lifetime (RUL) of degraded power MOSFETs is estimated through classical least-squares algorithm run on experimental data filtered by Kalman Filter which deals with the measurement noise and model uncertainties. The essential advantage of the proposed method is that it does not require junction temperature information. The RUL estimation with limited field data is demonstrated on a number of experimental results.

(Invited) Trench-Gated MOSFET Instability Caused by High Temperature Reverse-Bias Stress

The trench-gated MOSFET is widely used in power management applications because of its ultra-low on resistance [1]. Studies of trench-gate MOSFET reliability and degradation of blocking voltage and leakage current as well as edge termination effects are becoming increasingly important as the device dimensions shrink and its applications are diversified. The HTRB (high temperature reverse-bias) and HAST (highly accelerated temperature & humidity stress test) are often used in reliability assessment of planar discrete power MOSFETs [2] and are currently used in trench-gated MOSFET. The both HTRB stress and HAST stress apply a reverse bias voltage on the drain side with the source and gate grounded at elevated temperature in a MOSFET device. However, the HAST stress is at 85% HR relative humidity under pressure condition. The possible failure modes for HTRB and HAST stress are IDSS (drain to source) leakage current increase or shift, breakdown voltage shift or degradation, and Vth (threshold voltage) shift or instability. The failure mechanism under various failures is complex. They depend on not only device design and process, but also package process and its materials such as mold compound, as well as interaction between device and package. In this paper, we discuss the instability of n-channel trench-gated MOSFET under HTRB and HAST reliability stresses. The devices are packaged by using state-of-the-art “low pitch” wafer-level-chip-scale package (WLCSP) without the use of mold compound or leads frame. We have observed that the HTRB and HAST stress increases gate oxide interface trap density. However humid HAST stress is observed to further introduce mobile positive charge in the gate oxide of the trench-gated MOSFET. This positive charge is argued to comprise protons (H+s) [3]. The proton is generated through electric-field assisted interaction and hole injection into the gate oxide at the bottom of the trench. The mobility of these protons is observed to cause gate-voltage induced modulation in the threshold voltage and leakage current of the trench-gated MOSFET. In order to determine the mechanism by which H+s are introduced in the oxide, SEM inspection of the n-channel trench-gated MOSFET deprocessed to passivation showed the presence of passivation cracks in the device’s edge termination which cause moisture penetrated in the device during the HAST stress. Furthermore, the experimental and simulation results lead us to conclude that in this study we are observing negative bias temperature instability (NBTI) in a parasitic p-MOSFET structure arising at the bottom of the trench in an n-channel trench-gated MOSFET during HTRB stress [4]. The NBTI is enhanced by the presence of moisture in the oxide.

Power voltage-current converter using quasi-complementary MOSFET current mirrors

A voltage current convertor is described having a quasi complementary class AB architecture that is particularly suited to implementation using discrete power MOSFETs. High-voltage mirror designs are presented, enabling the construction of sources with kilovolt compliance range, tens of watts of output power and greater than 100 kHz bandwidth. GΩ output impedance and distortion below 1% can be obtained with no trimming or transistor matching.

A 1200V High-Power Driver IC with Multi-Chip Mounting for Strong HEVs

1200V high-power IC for Hybrid Electric Vehicles (HEVs) was developed for the first time. This IC consists of the 30V lower and upper arm ICs fabricated by Silicon On Insulator (SOI) process, 1200V discrete power MOSFETs for level shift circuit, and 30V discrete power MOSFETs for the output stage. The chips were mounted by BGA (Ball Grid Array) technology with Pb free solder balls. With these technologies, the high blocking voltage of 1200V was achieved without a special high-voltage IC process. In addition, the soft and low loss switching was realized by combination of high power output stage and the soft gate circuits, which this power IC can drive an Insulated Gate Bipolar Transistor (IGBT) even for over 100kW class inverter.

Advanced power semiconductors and ICs for DC/DC converter applications

This paper describes recent advances in power semiconductor devices, integrated circuits, and packages for DC/DC converter applications. Special emphasis is placed on the latest discrete power MOSFET devices and packages. Features and trends in ICs for control of synchronous buck converters are highlighted as well. The paper will also cover a new class of miniaturized hybrid assembly that sets new efficiency standards for high current low output voltage applications.

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N 2O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N 2O nitridation piles up in the oxide at the Si–SiO 2 interface regardless of nitridation time. The results obtained show improved breakdown field ( E bd), and charge-to-breakdown ( Q bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density ( D it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.

Determining the drain doping in DMOS transistors using the hump in the leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers. >