Direct Power Injection Method Research Articles

Examining the Thermal Stress Effect of Electromagnetic Susceptibility of Automotive CAN Controller

CAN controllers are responsible for the processing and transmission of CAN signals, which render them indispensable electronic devices in automotive cyber-physical systems. SJA1000T is one of the most common CAN communication chips which can be implemented through the use of bulk silicon CMOS technology. A susceptibility test platform is built based on the direct power injection method following IEC62132-4 to explore the electromagnetic susceptibility characteristics and the effects of thermal stress on CAN controller. Test results show that the susceptibility threshold curve is corresponded directly to frequency and temperature. The influence of thermal stress on the input and output characteristics of MOSFET is simulated and analyzed to verify the anti-interference ability and reduced reliability of the chip in a high temperature environment.

Investigation of Semi-Rigid Coaxial Test Probes as RF Injection Devices for Immunity Tests at PCB Level

This work investigates the performance of RF immunity procedures exploiting semi-rigid coaxial test probes as coupling devices to inject continuous wave (CW) RF power into the outlets of Integrated Circuits (ICs). Two solutions are presented, both offering the advantage with respect to the traditional direct power injection method, to run the test without removing the IC from its actual PCB. The first procedure resorts to near-field coupling to inject the noise into an interconnecting trace. The second procedure requires metallic contact between the probe tip and the injection point (e.g., a via or an IC pin). Specific figures of merit, such as coupling and power efficiency, test repeatability and intrusiveness, sensitivity to setup parameters and lateral spatial resolution, are introduced and used to ascertain the effectiveness of the proposed procedures. To this end, both numerical simulations and measurements were carried out on several PCBs. Feasibility of the proposed immunity procedures is eventually proven by an application example, involving a thermal sensor as device under test.

An ICIM-CI-T Model for EMI Prediction of IO Element on Typical FPGA With Temperature Effect Considered

In this paper, the electromagnetic interference and temperature coupling on MOS transistor is analyzed. The temperature controlled platform that combined with the standardized direct power injection method is designed for experimental measurement. Then the temperature effect on MOS device is considered into the conducted electromagnetic immunity model of input/output element (IOE) for typical field programmable gate array. Meanwhile, the proposed immunity model ICIM-CI-T (integrated circuits immunity model-conducted immunity-temperature), which is based on ICIM-CI, is built to predict the influence of thermal effect on the electromagnetic immunity of IOE. Finally, the validation of the ICIM-CI-T model is verified by experimental measurements, and both simulation and measurement results fit very well at different temperatures. Moreover, it is also observed that temperature exerts different effects on the immunity characteristic of IOE with the change of radio frequency interference frequency.

Susceptibility of flash ADCs to electromagnetic interference

Integrated devices acquiring environmental, industrial or biomedical signals are ubiquitous and require sensor systems to be situated in electromagnetically hostile environments and continue to operate reliably. The susceptibility to injected electromagnetic interference by an 8-bit flash Analog to Digital Converter (ADC) was measured using the direct power injection method (IEC 62132-4). The analysis of the immunity results and the susceptibility of the internal structure of the device are presented. Measurements show that the supply port is immune to interference but the analog input and reference voltage input ports are quite susceptible. Better understanding of the susceptibility of a flash ADC to EMI enables designers to reduce the cost of preventative measures implemented at the system level and improve the reliability of sensor systems.

Nonlinear Behavior Immunity Modeling of an LDO Voltage Regulator Under Conducted EMI

This paper presents a nonlinear behavior modeling method committed to the immunity of low-dropout (LDO) voltage regulator to conducted electromagnetic interference (EMI). A nonlinear behavior model is proposed to predict the immunity of LDOs, where the nonlinear characteristics of an LDO voltage regulator are described as a cascade of Taylor series and linear filter system. A test printed circuit board (PCB), using the direct power injection (DPI) method, is designed up to 2 GHz to measure the immunity of LDOs. A nonlinear behavior model, lump-parameter models of discrete components on PCB extracted from S -parameter measurement, and DPI method are used to predict the immunity of an LDO voltage regulator. The comparison of immunity between simulation and measurement shows that the model has a good fit up to 2 GHz.

다양한 PCB의 전원 분배 망에서의 PLL의 전자기 내성 검증

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.

High-Voltage PMOS Transistor Model for Prediction of Susceptibility to Conducted Interference

This paper presents a circuit-based high-voltage p-channel metal-oxide-semiconductor (HV-PMOS) transistor model that includes a vertical parasitic p-n-p bipolar transistor and a procedure for extraction of its model parameters. HV-PMOS transistors are subjected to conducted radio frequency (RF) interference at the source pin by using the direct power-injection method. The results reveal complex behavior when the power level of RF interference is varied. This behavior is caused by both nonlinear characteristics of the intrinsic MOS transistor and turn-on of the parasitic p-n-p bipolar transistor at higher RF power levels. The impact of strong conducted RF interference up to 20 dBm is modeled accurately in the frequency range from 1 MHz up to 1 GHz.