High-Voltage PMOS Transistor Model for Prediction of Susceptibility to Conducted Interference

Abstract

This paper presents a circuit-based high-voltage p-channel metal-oxide-semiconductor (HV-PMOS) transistor model that includes a vertical parasitic p-n-p bipolar transistor and a procedure for extraction of its model parameters. HV-PMOS transistors are subjected to conducted radio frequency (RF) interference at the source pin by using the direct power-injection method. The results reveal complex behavior when the power level of RF interference is varied. This behavior is caused by both nonlinear characteristics of the intrinsic MOS transistor and turn-on of the parasitic p-n-p bipolar transistor at higher RF power levels. The impact of strong conducted RF interference up to 20 dBm is modeled accurately in the frequency range from 1 MHz up to 1 GHz.