Direct Injection-locked Frequency Divider Research Articles

W-band CMOS direct injection-locked frequency divider with 23.5-GHz locking range using distributed LC network and power matching and body bias techniques

A low power and wide locking-range W-band (75–110 GHz) divide-by-2 direct injection-locked frequency-divider (DILFD) using standard 90 nm CMOS technology is reported. To enhance the operation frequency, distributed LC network is used as the load of the crossed-coupled transistors. To improve the input sensitivity, a power matching network is included at the injection terminal of the switch transistor. In addition, to enhance the frequency locking range, body bias technique (i.e. a body resistor in conjunction with a zero body-source bias) is adopted in the switch transistor to reduce its threshold voltage. The result shows that a wide locking-range of 23.5 GHz [from 69.5 to 93 GHz (28.9%)], covering the 77–81-GHz-band for short range automotive radar system and 81–86-GHz-band for high-speed point-to-point wireless communication access system, was achieved. The DILFD can be operated at a low input power of − 35 dBm, one of the best input sensitivity ever reported for a W-band CMOS divider. The power consumption of the DILFD was only 3 mW from a 0.7 V power supply. The chip area was only 0.76 × 0.66 mm2 excluding the test pads.

Modified Inductive Peaking Direct Injection ILFD With Multi-Coupled Coils

In this letter, we present the design of a fully differential direct injection locked frequency divider (D-ILFD) in 65 nm CMOS process. Based on strong coupling of multi-coupled coils, we propose a modified inductive peaking in the D-ILFD to improve the locking range with a compact core area. The proposed injection locked frequency divide-by-2 divider demonstrates an operation frequency range of 6.7 GHz for a low injected power of -8 dBm and single-ended output power of -4 dBm. With a supply voltage of 1 V, the power consumption of the D-ILFD is 2.5 mW and the power efficiency (Pout/PDC) is 8.3%.

Low‐power 25.4–33.5 GHz programmable multi‐modulus frequency divider

A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided-by-8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dual-modulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm.

A Ka-band wide locking range frequency divider with high injection sensitivity

This paper proposes a direct injection-locked frequency divider (ILFD) with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of −3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V The chip area including the pads is 0.5 × 0.5 mm2.

A 30GHz Wideband CMOS Injection-Locked Frequency Divider for 60GHz Transceiver

In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.

CMOS direct injection-locked frequency divider (3.55 mW 80 GHz) with 26.3% locking range using distributed LC tank and body bias techniques

A 3.55-mW 80-GHz complementary metal-oxide-semiconductor (CMOS) divide-by-2 direct injection-locked frequency divider (DILFD) using distributed inductance-capacitance (LC) tank and body bias techniques for operation frequency and locking-range enhancement is demonstrated.Compared with the traditional LC tank, the distributed LC tank significantly decreases the equivalent LC and C values. This in turn results in an increase of the operation frequency and the locking range. In addition, trans-conductance (gm) of the injection transistor can be improved by body bias due to the reduction of its threshold voltage. This in turn results in an increase of the locking range (6.2 GHz in simulation). Furthermore, power consumption is reduced by eliminating the head current source in the traditional DILFD. Measurement result shows the proposed DILFD achieved a state-of-the-art 26.3% (61.5–80.1 GHz) locking range and an excellent output phase-noise of −128.69 dBc/Hz at 1 MHz offset. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2694–2697, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26333

A $V$-Band Divide-by-4 Direct Injection-Locked Frequency Divider in 0.18-$\mu{\hbox {m}}$ CMOS

In this paper, a novel circuit topology of a CMOS divide-by-4 direct injection-locked frequency divider is presented for millimeter-wave applications. To enhance the locking range for circuit operations with a division ratio of 4, a series peaking technique is introduced in the proposed divider structure such that improved input injection efficiency can be achieved. Using a standard 0.18-μm CMOS process, a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band frequency divider is fabricated for demonstration. Operated at a supply voltage of 1.8 V, the divider core consumes a dc power of 12.6 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range of 2.44 GHz in the vicinity of 60 GHz. The measured output power and locked phase noise at 1-MHz offset are -7 dBm and -133 dBc/Hz, respectively.

A V-Band CMOS Direct Injection-Locked Frequency Divider Using Forward Body Bias Technology

This letter presents a V-band direct injection-locked frequency divider (ILFD) using forward body bias technology. The divider is implemented in a 0.13 μm CMOS process. The measurements show that the free-running frequency of the divider is 28.67 GHz, the total locking range is 16.2% at 58 GHz with 3.93 mW from a low supply voltage of 0.7 V, and the measured phase noise of the divider is -123.5 dBc/Hz at 500 KHz offset. The output power of the divider is higher than -9 dBm from 54 to 61 GHz, and a good figure of merit is achieved.

A CMOS Direct Injection-Locked Frequency Divider With High Division Ratios

A CMOS injection-locked frequency divider (ILFD) with high division ratios and high frequency operation is presented. It consists of a ring oscillator and injection capacitors. An input signal is directly injected through the capacitors into the feedback nodes of the ring oscillator. The proposed ILFD is fabricated in a 0.18 mum CMOS process and has a chip core size of 68 mum times 70 mum. It shows multiple division ratios of 3, 6, and 9. The operation frequency is from 2.2 to 30.95 GHz. At the maximum operation frequency, the ILFD has a locking range of 260 MHz with an input power of less than 0.25 dBm, a division ratio of 9, and a power consumption of 12.5 mW. The locking range increases up to 3.2 GHz as the division ratio and the operation frequency decrease.

A 58‐GHz wide‐locking range CMOS direct injection‐locked frequency divider using input‐power‐matching technique

AbstractA 58‐GHz (V‐band) CMOS direct injection‐locked frequency‐divider (DILFD) using input‐power‐matching technique for locking‐range enhancement is reported for the first time. In an input‐power‐matching technique, an inductive input‐matching‐network is added to the gate of the NMOS switch to optimize the input‐power‐matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9–58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input‐matching‐network for comparison. The chip area was only 0.585 × 0.492 mm2 excluding the test pads. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 685–689, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24158

77 GHz CMOS injection-locked Miller frequency divider

A 77 GHz injection-locked Miller frequency divider (ILMFD) is presented. The proposed architecture inserts a direct injection-locked frequency divider into the feedback loop of a Miller divider to achieve divide-by-three function. The overall chip size of the 0.13 µm CMOS ILMFD is 0.99×0.69 mm. The measured locking range is 2.2 GHz around 77 GHz without any frequency tuning.

Ring-Based Direct Injection-Locked Frequency Divider in Display Technology

This letter presents the first RF frequency divider on glass to demonstrate the feasibility of system on display (SoD). The frequency divider is developed in 1P2M 3 mum low-temperature polycrystalline silicon (LTPS) thin-film transistor technology. The core cell of the LTPS direct injection-locked frequency divider is the single stage ring oscillator. The additional cross-coupled transistor pair increases the phase shift of the ring oscillator to meet the oscillation condition. The maximum locking range of the LTPS frequency divider is 2 MHz, and it can be operated from 120 Hz to 8 MHz with frequency tuning. Operated at 10 V, the frequency divider consumes 1.8 mW of power. The area of the frequency divider circuitry is 2.13 times 2.6 mm.

A low‐power 63‐GHz CMOS direct injection‐locked frequency divider in 0.13‐μm CMOS technology

AbstractA low‐power 63‐GHz (V‐band) direct injection‐locked frequency‐divider (ILFD) using standard 0.13‐μm CMOS technology is reported. To reduce power consumption and enhance locking range, a PMOS switch directly coupled to the LC tank (output) of the ILFD is used to replace the traditional tail transistor for injection path. This ILFD architecture also features a very low input capacitance; thus, high operating frequency of 63 GHz can be achieved. This direct ILFD consumes 5.79 mW with locking range of 1.86 GHz (61.24–63.1 GHz). The chip area was only 0.585 × 0.38 mm2 excluding the test pads. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2581–2584, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23768

Design and Analysis of a Millimeter-Wave Direct Injection-Locked Frequency Divider With Large Frequency Locking Range

In this paper, direct injection-locked frequency dividers (ILFDs), which operate in the millimeter-wave (MMW) band, are analyzed. An analytically equivalent model of the direct ILFDs is developed, and important design guidelines for a large frequency locking range are obtained from it. These guidelines are: 1) maximize the quality factor of the passive load; 2) maintain low output amplitude; and 3) increase the dc overdrive voltage of the input device. A direct ILFD without varactors is designed and fabricated using a 0.13-mum bulk CMOS process to verify the developed model and design guidelines. A pMOS current source is used to restrict the output amplitude and to increase the dc overdrive voltage of the input device to achieve a large frequency locking range. The size of the input device is only 3.6 mum/0.12 mum and the measured frequency locking range is 13.6% at 70 GHz with a power consumption of 4.4 mW from a supply voltage of 1 V. In short, the proposed divider has the potential to be integrated into an MMW phase-locked loop system.

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-μm complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.