Diode-triggered Silicon-controlled Rectifier Research Articles

A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection.

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

A novel dual-directional DTSCR in twin-well process for ultra-low-voltage ESD protection

By embedding additional NPN- and PNP- type bipolar junction transistors into a diode-triggered silicon-controlled rectifier (DTSCR) with single-directional ESD protection, we propose and implement a novel dual-directional DTSCR (DDTSCR) by using the twin-well process in a 0.18-µm CMOS process that provides highly efficient ultra-low-voltage ESD protection. Compared to conventional DTSCRs, the failure current of the proposed DDTSCR increases from 4.5 A to 5.6 A, successfully passing the ESD level tests of human body model at 8 kV and machine model at 650 V. Owing to its unique structural design and metal routing, the ESD protection efficiency of the DDTSCR is twice that of the DTSCR. By adopting a new E-shaped layout (DDTSCR-E), the failure current under positive stress can increase further to 6.6 A. In order to verify the ESD protection performance stabilization with different processes, the DDTSCR-E is fabricated in the 0.18-µm BCD, 0.18-µm and 21-nm CMOS processes, respectively. The trigger voltage of DDTSCR-E is found more stable than other ESD characteristics during the process migration. The high efficiency, the strong ESD robustness and the stable process migration make the proposed DDTSCR a promising ESD protection device for ultra-low-voltage integrated circuits.

High Area Efficiency Bidirectional Silicon-Controlled Rectifier for Low-Voltage Electrostatic Discharge Protection

Continuously scaling down and decreasing operation voltages of ICs, from the 5 V TTL-compatible voltage to 3.3 V, then 1.2 V, and now 0.8 V for low-power ICs, results in more stringent electrostatic discharge protection design requirements, such as a narrow ESD design window, low operation voltage, and high ESD robustness. Based on traditional diode string and diode-triggered silicon-controlled rectifiers, an enhanced diode-triggered silicon-controlled rectifier is proposed to meet the requirements of low-voltage integrated circuits as bidirectional electrostatic discharge protection. The new device employs an additional PMOS and NMOS in the N-well and P-well, respectively, to offer additional current paths along the surface to significantly enhance its robustness. TCAD simulation shows that the device is triggered by both the diode strings and embedded MOS, making the device turn on faster and the current distribution more uniform during the ON state owing to the additional surface current paths. The proposed new device has excellent dual-directional ESD protection performance with a figure of merit of 4.01 mA/um2, which is about a 71% improvement compared with the conventional diode-triggered silicon-controlled rectifier. It also has higher area efficiency, lower trigger voltage, lower current leakage, and a faster turn-on speed. The proposed enhanced diode-triggered silicon-controlled rectifier is an attractive ESD protection solution for ultra-low-voltage ICs.

Tunnel Field-Effect Transistor Triggered Silicon-Controlled Rectifier

In this article, a tunnel field-effect transistor (TFET) triggered silicon-controlled rectifier (SCR) device is proposed. A TFET is embedded into the SCR enabling an early carrier’s transportation through the n-well/p-well reverse-biased junction. This accelerates the junction breakdown and helps to establish the SCR’s positive feedback regeneration. The applications of the TFET-triggered SCR (TTSCR) in electrostatic discharge (ESD) protection are explored and the electrical characteristics are investigated. Moreover, the impact of the device structure on the device performance is discussed. The principle of the proposed device is verified using technology computer-aided design (TCAD) simulation. The simulation results show that compared to the prevalent diode-triggered SCR, the proposed device has a small layout area, a low leakage current, and a low overshoot voltage.

A Novel DTSCR With Embedded MOS and Island Diodes for ESD Protection of High-Speed ICs

A novel diode-triggered silicon-controlled rectifier with embedded MOS and island diodes (DTSCR-EMOS-ID) is proposed and investigated. The DTSCR-EMOS-ID was fabricated in 0.18-μm and 22-nm CMOS processes for verifying the process transplantation. The fabricated DTSCR-EMOS-ID presents a low trigger voltage of 1.3 V, a small turn-on resistance of 8 mΩ/μm and a small parasitic capacitance of 43 fF. Meanwhile, the effective failure current and response time of DTSCR-EMOS-ID are optimized to 4.3 A and 3.6 ns, respectively. The DTSCR-EMOS-ID shows much better ESD performance than the conventional LVTSCR and DTSCR fabricated in the same process, which can be attributed to the diode triggering, gate coupling and large injection effects. Moreover, the TCAD simulation results of DTSCR-EMOS-ID agree well with the transmission line pulse testing results, further confirming that the proposed DTSCR-EMOS-ID can be widely used as an effective ESD protection device for high-speed ICs, without the limitation of the fabrication process.

A Millimeter-Wave Broadband Reflectionless ESD Protection Device

In this letter, a broadband millimeter-wave (mm-wave) electrostatic discharge (ESD) protection structure is proposed and verified in a 40-nm CMOS process. The main ESD protection device is a diode-triggered silicon-controlled rectifier (DTSCR) with a tunable trigger voltage. Two weakly-coupled inductors are embedded to increase the operating bandwidth. Both theoretical analysis and simulation results show that a low coupling factor is necessary to obtain the wideband characteristic. The proposed design exhibits good ESD protection performance (HBM robustness >1.875kV), fast turn-on speed, wideband reflectionless characteristic (S11<–15dB within 33.6-50GHz), tunable trigger voltage and low leakage current. Therefore, this new device is suitable for ESD protection of input/output (I/O) pads in mm-wave-communication applications.

Compact and Fast Response Dual-Directional SCR for Nanoscale ESD Protection Engineering

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection.

Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs

A gate-assisted and diode-triggered silicon controlled rectifier with the waffle layout (GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the conventional diode-triggered silicon controlled rectifier (DTSCR), the electrostatic discharge (ESD) performance of the GDTSCR-WL can be used to optimize remarkably, especially for the parasitic capacitance, clamping voltage (V C), and current handling ability. By further introducing the gate-assisted trigger effect, the GDTSCR-WL can discharge the ESD-induced current more quickly. The technology computer aided design (TCAD) simulations and electrical test results indicate that the GDTSCR-WL has extraordinary ESD performance, such as a V C of 1.24 V, a turn-on resistance of 0.14 Ω, and the large figure of merit of 5.76 mA μm−2, outperforming dual-diode string and DTSCR. Moreover, by adjusting the width W 1 and space W 2 of diode blocks with the waffle layout, the capacitance of the GDTSCR-WL can be continuously decreased from 140 to 92 fF. The optimized GDTSCR-WL with a small capacitance can pass the 8 kV human body model test, providing an efficient and optional solution for high-speed input/output ESD protection of on-chip ICs.

Analyze Scalable Sudoku-Type DTSCR ESD Protection Array Structures in 22nm FDSOI

This paper reports the design and analysis of scalable Sudoku-type diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharge (ESD) protection structures fabricated in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI) technology. 3D TCAD and ESD testing confirm that the Sudoku DTSCR ESD structures can dramatically improve the ESD area efficiency. Transmission line pulse (TLP) measurement shows a high ESD area efficiency of 6.47mA/mum2 for Sudoku-DTSCR, 64.6% improvement over traditional finger-DTSCR structure. A scalability model was derived as design guidelines for optimizing Sudoku DTSCR ESD protection array structures.

A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transient voltage peaking phenomena of diode-based ESD protection structures under CDM stressing. The study of a set of diode, diode-string and diode-triggered silicon-controlled rectifier (DTSCR) ESD protection structures, fabricated in a 28nm CMOS process, reveals that the inductive impedance along the ESD discharging path may be the root cause of voltage peaking under CDM stressing. The observation provides the design insights overcoming the voltage peaking problem in ESD protection designs before complicate CDM package level testing.

New Diode-Triggered Silicon-Controlled Rectifier for Robust Electrostatic Discharge Protection at High Temperatures

The diode-triggered silicon-controlled rectifier (DTSCR) is an important device for the electrostatic discharge (ESD) protection of low-voltage integrated circuits, and its trigger voltage is determined by the forward turn-on voltage of diode string and the voltage drops on the parasitic resistors of metal interconnects. For the conventional DTSCR, the voltage drops on the parasitic resistors are often negligible so its triggering voltage is mainly determined by the forward turn-on voltage of diode string, which decreases with increasing temperature due to the inherited negative temperature coefficient. In this paper, an improved and novel device called thermal-stable DTSCR (TSDTSCR) is proposed to offer an improved ESD protection stability at elevated temperatures. This is done by changing and optimizing the 3-D layout. In particular, the experimental results show that the trigger voltage drop of the TSDTSCR can be reduced to 13.5% at 125 °C, comparing to 27.18% of the DTSCR. The holding voltage of the TSDTSCR is also more stable than that of the DTSCR over a wide range of temperatures.

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection

A conventional diode-triggered silicon-controlled rectifier (DTSCR) structure with a layout strategy for electrostatic discharge (ESD) protection is presented and confirmed in a 65-nm CMOS technology. The modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing (TLP)/very fast transmission line pulsing (VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model (CDM) event.

28 nm CMOS process ESD protection based on diode-triggered silicon controlled rectifier

The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide. In this work, we had developed a two-dimensional diode-triggered silicon-controlled rectifier (TD-DTSCR) structure to cope with the narrowed ESD design window in the 28nm CMOS technology. A sufficient large SCR trigger voltage was obtained by directing the triggering current to both longitude and lateral directions, through two parasitic diodes and the P-Well, so as to save the chip area for realization. Optimization was done by varying several device parameters and the best ESD robustness obtained was 53.7mA/μm which was about 65% larger than that of a simple SCR with the same width of 30μm and realized using the same technology. Failure analysis was also conducted to identify the possible weak spots of the proposed structure.

New triggering-speed-characterization method for diode-triggered SCR using TLP

The key parameters in the optimization of the Diode Triggered Silicon-Controlled Rectifier (DTSCR) as a RF ESD protection, are the turn-on time and the trigger-voltage overshoots seen before the SCR turns on, during very fast ESD transients [1]. But at this time, there is no normalized method to evaluate and report the ESD device turn-on speed [2]. Such a method would be required to effectively compare device performance. In this work a new method, based on stored-charge, is investigated to characterize the triggering speed of DTSCR using Transmission Line Pulsing (TLP) measurements.

Insight into multiple-triggering effect in DTSCRs for ESD protection**Project supported by the Beijing Natural Science Foundation, China (No. 4162030).

The diode-triggered silicon-controlled rectifier (DTSCR) is widely used for electrostatic discharge (ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse (TLP) test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multiple-triggering effect.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress**Project supported by the Beijing Municipal Natural Science Foundation, China (Grant No. 4162030) and the National Science and Technology Major Project of China (Grant No. 2013ZX02303002).

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing (TLP) test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal–oxide–semiconductor (CMOS) process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Minimizing Multiple Triggering Effect in Diode-Triggered Silicon-Controlled Rectifiers for ESD Protection Applications

The diode-triggered silicon-controlled rectifier (DTSCR) is frequently used for low-voltage electrostatic discharge (ESD) protection applications, but such a device can exhibit two snapbacks and consequently can possess an undesirable large trigger voltage. This letter investigates the mechanism underlying the DTSCR's multiple triggering. An improved DTSCR for reducing the second trigger voltage and increasing the ESD safe margin is proposed and verified in a 65-nm complementary metal-oxide-semiconductor process. The improved DTSCR's turn-on characteristic is also discussed.

Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection

Diode-triggered silicon-controlled rectifiers (DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found with STI-bound diodes. A DTSCR with only STI-bound trigger diodes has a lower leakage current. Therefore, DTSCRs with different trigger diode configurations may be suitable for different applications, e.g., high speed or low power.

Low-leakage diode-triggered silicon controlled rectifier for electrostatic discharge protection in 0.18-μm CMOS process

A diode-triggered silicon controlled rectifier (DTSCR) is being developed as an electrostatic discharge (ESD) protection device for low voltage applications. However, DTSCR leaks high current during normal operation due to the Darlington effect of the triggering-assist diode string. In this study, two types of diode string triggered SCRs are designed for low leakage consideration; the modified diode string and composite polysilicon diode string triggered SCRs (MDTSCR & PDTSCR). Compared with the conventional DTSCR (CDTSCR), the MDTSCR has a much lower substrate leakage current with a relatively large silicon cost, and the PDTSCR has a much lower substrate leakage current with similar area and shows good leakage performance at a high temperature. Other DTSCR ESD properties are also investigated, especially regarding their layout, triggering voltage and failure current.

Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies

A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f/sub Tmax/=45 GHz in BiCMOS 0.35-/spl mu/m LNA input) and thin gate oxides (e.g., t/sub ox/=1.7 nm in CMOS 0.09-/spl mu/m high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.