Diode-connected MOS Transistor Research Articles

A 1 V -21 dBm threshold voltage compensated rectifier for radio frequency energy harvesting

Due to the limitations of battery life and capacity, power supply has been the bottleneck for scaling of a wireless sensor network in thousands or millions of nodes. RF energy harvester (RFEH) is a promising solution to power up sensors and wireless devices due to increasing accessibility of RF energy sources, better silicon integration of the harvester circuit and compatibility with wireless networks. One of the significant limitations of RF energy harvester is low power efficiency rectifier where the main function of the micropower rectifier is to convert RF energy into DC energy. To achieve higher power conversion energy (PCE), this paper presents a five-stage charge pump rectifier, with implementation of diode-connected MOS transistors and an auxiliary circuit to produce compensation voltage to the charge pump to achieve higher efficiency over a wide input range. This work is designed and implemented using 130nm CMOS technology and achieved a wide input power range of 15 dBm with efficiency higher than 20%; and at -21 dBm sensitivity for 1V output is achieved while driving 1 MΩ load at 920MHz.

Reduction of NEP variations for terahertz detectors using Schottky barrier diodes in CMOS

Variations of low-frequency noise including flicker and Lorentzian spectra are the dominant source of variation of noise equivalent power (NEP) for terahertz detectors using diode-connected N-type MOS (NMOS) transistors. The low-frequency noise of Schottky diodes fabricated in the same CMOS process as the NMOS detectors are dominated by generation and recombination noise. At 1 MHz modulation frequency, the noise of Schottky barrier diodes (SBDs) and its variation are ∼2× lower than those of diode-connected NMOS transistors. It should be possible to reduce the variation of NEP by ∼2× using Schottky diode detectors modulated at 1 MHz.

2.4 GHz CMOS self‐biased power amplifier with embedded diode lineariser

A high-linearity CMOS power amplifier (PA) operating at 2.4 GHz with an integrated diode lineariser is presented. A diode-connected N-type MOS transistor is used to increase the V gs of the power transistor as input power increases for linearity improvement. The CMOS PA fabricated in 180 nm CMOS technology achieved 32 dB small signal gain, 30.2 dBm P sat, 28.2 dBm P 1 dB, and a 31.1% peak power added efficiency. By adopting the proposed diode lineariser, the output 1 dB is improved from 24.9 to 28.2 dBm.

A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer

A high-linearity CMOS power amplifier (PA) operating at 2.45GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance (Cgs) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2dB, a maximum output power of 30.7dBm with 29% of peak power added efficiency (PAE) and −30dBc third-order intermodulation (IMD3) product at 26.4dBm output power, reaching to excellent tradeoffs between efficiency and linearity.

Electro-thermal characterization of a differential temperature sensor in a 65 nm CMOS IC: Applications to gain monitoring in RF amplifiers

This paper reports on the design solutions and the different measurements we have done in order to characterize the thermal coupling and the performance of differential temperature sensors embedded in an integrated circuit implemented in a 65nm CMOS technology. The on-chip temperature increases have been generated using diode-connected MOS transistors behaving as heat sources. Temperature measurements performed with the embedded sensor are corroborated with an infra-red camera and a laser interferometer used as thermometer. A 2GHz linear power amplifier (PA) is as well embedded in the same silicon die. In this paper we show that temperature measurements performed with the embedded temperature sensor can be used to monitor the PA DC behavior and RF activity.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

A High Efficiency Orthogonally Switching Passive Charge Pump Rectifier for Energy Harvesters

The design and analytical modeling of a high efficiency energy harvester comprising a passive voltage-boosting network (VBN) and a switching charge pump rectifier (CPR) is presented in this paper. To improve the power conversion efficiency (PCE), the VBN increases the voltage at the input of the CPR and provides control signals for switching. Unlike traditional Schottky and diode-connected MOS transistor rectifiers, the proposed orthogonally switching CPR (OS-CPR) comprises MOS transistors as voltage-controlled switches. Analytical models for the OS-CPR are developed and presented. Circuit-level optimization techniques are employed to reduce conduction and switching losses. Simulated in a 90 nm standard CMOS technology (IBM 9RF), a 5-stage 915 MHz OS-CPR achieves a dc voltage of 1.35 V and a PCE of 11.9% with a 1 MΩ load at -18.2 dBm available input power ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S,AV</sub> ). To show technology scalability of the design, the OS-CPR is also validated using AMS 0.18 μm high-voltage (HV) CMOS technology. When benchmarked with traditional rectifiers, the OS-CPR (under similar conditions) achieves a higher PCE and a higher output dc voltage. The OS-CPR is easily scalable to operate over multiple sub-GHz ISM frequency bands.

High Area-Efficient ESD Clamp Circuit With Equivalent $RC$-Based Detection Mechanism in a 65-nm CMOS Process

A power-rail electrostatic discharge (ESD) clamp circuit realized with ESD clamp device drawn in the layout style of big field-effect transistor (BigFET), and with parasitic diode of BigFET as a part of ESD-transient detection mechanism, is proposed and verified in a 65-nm 1.2-V CMOS process. Skillfully utilizing the diode-connected MOS transistor as the equivalent large resistor and the parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> -based ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by ~82%, as compared to the traditional <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> -based ESD-transient detection circuit. From the measured results, the new proposed power-rail ESD clamp circuit with body effect of ESD clamp device can perform adjustable holding voltage under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on under fast power-on and transient noise conditions.

A novel ultra low power ASK demodulator for a passive UHF RFID tag compatible with C1 G2 EPC standard protocol

In order to reduce the power consumption of RFID tags and increase the reading range of RFID systems, this paper proposes an ASK demodulator that uses a new approach to reduce the threshold voltage of diode connected MOS transistors as an obstacle in the design of the envelope detector. Also, an ultra low power comparator is used for further power reduction. This circuit has been simulated in a 0.18 μm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol emphasizing on the reduction of power consumption. The proposed circuit can correctly demodulate the minimum input RF signal amplitude of 180 mV for modulation depths of 55---100 % with 40---160 kb/s data rates. A total power consumption of less than 290 nW is achieved at a 1.2 V power supply. Effects of the input signal additive white noise as well as the process and temperature variations on the signal demodulation is also investigated in this paper.

A Model for MOS Diodes With $V_{\rm th}$ Cancellation in RFID Rectifiers

A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a design procedure for the optimization of the power conversion efficiency (PCE) of a bridge rectifier with ITC MOS diodes was developed based on the model. A rectifier was designed and implemented in an austriamicrosystems 0.35-μm CMOS process, and Cadence simulation results of the PCE and the voltage conversion efficiency show good agreement with the model.

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices.

A High PSRR Bandgap Voltage Reference with Virtually Diode-Connected MOS Transistors

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86dB and for the temperature range from -55°C to 125°C, the variation of the output reference voltage is less than 66ppm/°C.

New design of RF rectifier for passive UHF RFID transponders

A novel diode-connected MOS transistor for ultra-high-frequency (UHF) micro-power rectifiers was presented, and a high efficiency N-stage charge pump voltage rectifier based on this new diode-connected MOS transistor was designed and implemented. The new diode-connected MOS transistor and the rectifier are designed and fabricated in SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The structure design of the new diode achieved 315 mV turn-on voltage, and 415 nA reverse saturation leakage current. Compared with traditional rectifier, the rectifier using the presented diode-connected MOS has higher power conversion efficiency (PCE), higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the amplitude ranging from 0.8 to 1.8 V, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.02 V, and its ripple coefficients are less than 1%.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF–DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mum 2P4M CMOS technology. The whole chip occupies a die area of 490 times 780 mum2 and consumes only 2.1 muW in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a -14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Low voltage current mirrors with enhanced bandwidth

This paper presents an improved low voltage cascode and flipped voltage follower (FVF) based current mirror with the enhancement of the bandwidth obtained by using a compensation resistor between the gates of the primary transistor pair. In this technique a carefully determined resistance is used in the diode connected MOS transistor of the current mirror for enhancing the bandwidth. Active realization of the compensation resistance using MOS operating in the triode region has also been applied to both the cascode and FVF based current mirror circuits. The proposed circuits have been simulated using PSpice for 0.25 μm CMOS technology and the obtained results are compared with their uncompensated topologies to show their effectiveness.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis