Diminished-1 Modulo Research Articles

Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder

Residue Number System has to carry free operation and its various applications like digital signal processing, multimedia, security purpose, and medical perception. Removes of the redundant logic operation require the group carry selection logic which is dependent on Parallel Prefix Adder design. Therefore the logic operation of the preprocessing unit of PPA is simplified form to save logic resources. This modified parallel prefix adder consumes less area as compared to the existing design. In this paper, we propose the parallel architecture based on a parallel prefix tree is helpful for computation at higher speed operation. The reported design consumes 24.1% more area and 26.4% more power compare to THE proposed parallel prefix adder design. The proposed PPA design using modified carry computation algorithm and reported design used diminished-1 modulo 2n+1 adder structure is presented. A presented modulo adder design using the proposed parallel prefix adder and improved carry computation used in the previously proposed design. The proposed diminished-1 modulo (2n +1) adder design shows a 24.5% saving in area-delay-product (ADP).

Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry

Addition is the most basic operation of computing based on a bit system. There are various addition algorithms considering multiple number systems and hardware, and studies for a more efficient addition are still ongoing. Quantum computing based on qubits as the information unit asks for the design of a new addition because it is, physically, wholly different from the existing frequency-based computing in which the minimum information unit is a bit. In this paper, we propose an efficient quantum circuit of modular addition, which reduces the number of gates and the depth. The proposed modular addition is for the Galois Field GF(2n−1), which is important as a finite field basis in various domains, such as cryptography. Its design principle was from the ripple carry addition (RCA) algorithm, which is the most widely used in existing computers. However, unlike conventional RCA, the storage of the final carry is not needed due to modifying existing diminished-1 modulo 2n−1 adders. Our proposed adder can produce modulo sum within the range 0,2n−2 by fewer qubits and less depth. For comparison, we analyzed the proposed quantum addition circuit over GF(2n−1) and the previous quantum modular addition circuit for the performance of the number of qubits, the number of gates, and the depth, and simulated it with IBM’s simulator ProjectQ.

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder

Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

On the Diminished-1 Modulo 2n+1 Addition and Subtraction

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

Diminished-1 multiplier using modulo adder

In this work Modulo multiplier offers higher computational speed than a normal multiplier. It is frequently used in data security and residue number system. The modulo 122n+1"> has three basic blocks-partial product generation block, inverted end around carry adder tree block and diminished-1 modulo 122n+1"> adder block. The result and an operand use weighted representation and others uses the diminished-1 for the modulo multiplier. The multipliers receive full inputs and avoid (n+1) bits circuits due to diminished-1 number representation. In this work, proposed modulo 122n+1"> multiplier with modified diminished-1 modulo 122n+1"> adder which is based on ripple carry adder. The proposed design saves significant area and power as compared to the reported one with little increment in delay.

Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

In this brief, we proposed improved area-efficient weighted modulo 2n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n - 1} produced by existing diminished-1 modulo 2n + 1 adders. We have implemented the proposed adders using 0.13-?m CMOS technology, and the area required for our adders is lesser than previously reported weighted modulo 2n + 1 adders with the same delay constraints.

Efficient modulo 2n+1 multipliers for diminished-1 representation

An efficient architecture for diminished-1 modulo (2n+1) multipliers is described. The new architecture is built using a pure radix-4 Booth recoding block, an inverted end-around-carry carry save adder tree and a final diminished-1 adder. Although one correction term is used, the complexity of the circuit is very simple. There are n/2 partial products (PP), one simple correction term and one constant, each one n bits wide. The new multipliers can handle zero inputs and results. The analytical and experimental results indicate that the new multipliers offer better speed and more compact than previously published solutions.

Fast modulo [formula omitted] multi-operand adders and residue generators

In this manuscript novel architectures for modulo 2 n + 1 multi-operand addition and residue generation are introduced. The proposed arithmetic components consist of a translation stage, an inverted end-around-carry carry-save-adder tree and an enhanced diminished-1 modulo 2 n + 1 adder. Qualitative and quantitative results indicate that the proposed architectures result in significantly faster and in several cases smaller circuits than the previously proposed.

A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition

In this paper, it is shown that every architecture proposed for modulo 2n+1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo 2n+1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.

Efficient Diminished-1 Modulo 2^n+1 Multipliers

In this work, we propose a new algorithm for designing diminished-1 modulo 2/sup n/+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2/sup n/+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.

Diminished-1 modulo 2n+1 squarer design

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2n+1. To avoid using (n+1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2n+1 arithmetic applications. In the paper, for the first time in the open literature, the authors formally derive modulo 2n+1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full-and half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.