Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

Abstract

In this brief, we proposed improved area-efficient weighted modulo 2n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2n}, which is more than the range {0, 2n - 1} produced by existing diminished-1 modulo 2n + 1 adders. We have implemented the proposed adders using 0.13-?m CMOS technology, and the area required for our adders is lesser than previously reported weighted modulo 2n + 1 adders with the same delay constraints.