A selective low temperature polycrystalline silicon growth process has been developed and applied as a dielectric isolation technology to overcome the drawbacks of local oxidation of silicon (LOCOS) for high performance VLSI circuits. By selectively depositing polycrystalline silicon in nitride‐lined trenches using the system, comparatively planar dielectric isolation regions were created upon subsequent oxidation. Oxide‐masked test wafers with variable width trenches were used to exhibit selective polysilicon growth within a production chemical vapor deposition (CVD) reactor. Independent process parameters considered for selective growth optimization included prebake temperature, total reactor pressure, reactor temperature, wafer cleaning procedure, and in situ surface pretreatment procedure. The dependent response variables included surface morphology or planarity, crystallinity, selectivity, and growth rate. X‐ray diffraction, scanning electron microscope (SEM), and transmission electron microscope (TEM) were used to characterize deposition layer surface morphology and crystallinity. A filtered dilute etch combined with a 975°C, 50 Torr prebake effectively removed native oxides and left the surfaces relatively free of foreign matter detrimental to selectivity. Selectivity of approximately 2 particles/mm2 was achieved using this surface preparation technique within a class 1000 clean room. Furthermore, a pretreatment of the surface at 800°C promoted polycrystalline deposition when followed by a 700°C, atmospheric growth step. This investigation has led to a multiple‐step selective polysilicon growth (SPG) process which is repeatable and robust to normal laboratory variations. Advanced bipolar devices isolated by oxidized selective polysilicon trench refill have exhibited leakage currents of only 4.3 pA at a tub‐to‐tub voltage of 20 V. Trench dimensions isolating the active tubs were 2 μm deep, 1 μm wide, and 10 μm long.