Abstract
The improvement of latchup immunity in bulk, nonepitaxial CMOS with deep trench isolation has been demonstrated using numerical simulation. Through a proper design of trench dimensions and layout, it is shown that the holding voltage can be increased to a level above the power supply voltage (3.3 V in deep-submicrometer CMOS), yielding latchup-free CMOS even for nonepitaxial substrates. The holding voltage is strongly influenced by the current flow patterns in the conductivity-modulated well and substrate regions, which are affected by trench depth, layout parameters, and the tank and p/sup +//n/sup +/ emitter doping concentrations. The deep trench makes the current flow patterns two-dimensional, and this causes parametric dependencies that cannot be explained from simple trench-isolation techniques. Design issues that are unique to deep trench isolation have been identified.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
