Digital Error Research Articles

A robust regression-based linear model adjustment method for SAR interferogram stacking techniques

Differential interferometric synthetic aperture radar (DInSAR) is recognized as an effective remote-sensing technique for a variety of ground deformation mapping applications. Centimetre-level measurement accuracy can be achieved with the DInSAR technique. However, two key limitations – temporal decorrelation and phase delay due to atmospheric inhomogeneities – might decrease the accuracy of deformation measurements. To overcome such problems, interferogram stacking techniques, which extend the DInSAR technique, have been developed in recent years. In most implementations of such techniques, a so-called ‘linear model adjustment’ step is required to obtain the relative linear deformation rate and digital elevation model error from the double-differenced phase observations along the stack. In this step, since a non-linear system has to be resolved, the traditional least squares method cannot be directly applied. In order to overcome this problem, several methods have been developed in recent years. In this article, a new method has been developed to deal with the problem of linear model adjustment. This method repeatedly uses robust regression to resolve the non-linear system and is much easier to implement compared with other methods. This method is applied to both simulated and real data, and the results demonstrate that it can be efficiently used for linear model adjustment.

Preserving Imperfection: Assessing the Incidence of Digital Imaging Error in HathiTrust

AbstractLarge-scale digitization efforts by third-party firms are the subject of no small amount of controversy and criticism, as is especially the case with Google Books. This article reports some of the findings and important implications of a rigorous multi-year quantitative and qualitative assessment of the images representing a sizable proportion of the digital surrogates created by Google and deposited in the HathiTrust, which is one of the most important large-scale preservation initiatives to emerge in higher education in the past fifty years. The population of study described here consists of Englishlanguage books and serials published before 1923 that were scanned and processed by Google between 2004 and 2010. At the time the data for the study were gathered (2011), this population consisted of approximately 1.25 million volumes or roughly 12 percent of the HathiTrust corpus. The findings suggest that the imperfection of digital surrogates is an obvious and nearly ubiquitous feature of Google Books and that such imperfection has become and will remain firmly ensconced in collaborative preservation repositories.

A practical method for quickly determining electrode positions in high-density EEG studies

This report describes a simple and practical method for determining electrode positions in high-density EEG studies. This method reduces the number of electrodes for which accurate three-dimensional location must be measured, thus minimizing experimental set-up time and the possibility of digitization error. For each electrode cap, a reference data set is first established by placing the cap on a reference head and digitizing the 3-D position of each channel. A set of control channels are pre-selected that should be adequately distributed over the cap. A simple choice could be the standard 19 channels of the International 10–20 system or their closest substitutes. In a real experiment, only the 3-D positions of these control channels need to be measured and the position of each of the remaining channels are calculated from the position data of the same channels in the reference data set using a local transformation determined by the nearest three or four pairs of control channels. Six BioSemi ActiveTwo caps of different size and channel numbers were used to evaluate the method. Results show that the mean prediction error is about 2mm and is comparable with the residual uncertainty in direct position measurement using a Polhemus digitizer.

Addendum to: Assessment of Digital Image Correlation Measurement Errors: Methodology and Results [Experimental Mechanics 49(3)

The synthetic speckle images that were used to perform the simulations can be downloaded from the following website: h t t p : / / w w w. g d r 2 5 1 9. c n r s. f r / i m a g e _ d a t a b a s e / ExpMech2009_vol49-3_pp353-370/ The readers interested in assessing the metrological performance of their own DIC software are invited to download these files, to use them as input data and to discuss matters related to their results with the authors. Workgroup Metrology of the French CNRS research network 2519 Mesures de Champs et Identification en Mecanique des Solides / Full-field measurements and identification in solid mechanics

Off-line time calibration of the ATLAS RPC system

Resistive Plate Chambers (RPC's), operated in saturated avalanche regime, are used in the Muon Spectrometer of the ATLAS experiment to produce the first level of the muon trigger in the central region, |η| < 1.05. The trigger logic, based on a coincidence of hits in three layers of detector doublets, takes advantage of the very good time resolution of these detectors which allows to easily identify the LHC bunch crossing.The RPC readout electronics, based on a 320 MHz clock, allow to storea very granular time information, making the RPC system, potentially,the detector providing the most accurate time measurement in ATLAS.To fully exploit the intrinsic time resolution of detector and readoutelectronics, a careful calibration of the system is needed, involvingabout 330,000 channels. The ATLAS data recorded during 2011 in LHCp-p collisions at √s = 7 TeV have been used to show that,after applying an off-line calibration procedure, a time resolutionuniform over the entire detector and stable in time, can be reached.A simulation of the various contributions to the observed time offlight per single channel, implemented in the software for the ATLASsimulation, allows to understand the resolution measured in data. Thetime resolution is understood in terms of the intrinsic detectorresolution, the digitization error and the various components relevantat different levels of refinement of the time calibration procedure.Achieving the ultimate timing resolution of the RPC system is a verypowerful way of extending the physics potential of ATLAS experiment,for example, in searches for particles moving with low velocity fromthe interaction point. In addition, good time resolution may be a keyingredient for background rejection, which may become of overwhelmingimportance in future scenarios of increased LHC luminosity.

2D/3D registration algorithm for lung brachytherapy

A 2D∕3D registration algorithm is proposed for registering orthogonal x-ray images with a diagnostic CT volume for high dose rate (HDR) lung brachytherapy. The algorithm utilizes a rigid registration model based on a pixel∕voxel intensity matching approach. To achieve accurate registration, a robust similarity measure combining normalized mutual information, image gradient, and intensity difference was developed. The algorithm was validated using a simple body and anthropomorphic phantoms. Transfer catheters were placed inside the phantoms to simulate the unique image features observed during treatment. The algorithm sensitivity to various degrees of initial misregistration and to the presence of foreign objects, such as ECG leads, was evaluated. The mean registration error was 2.2 and 1.9 mm for the simple body and anthropomorphic phantoms, respectively. The error was comparable to the interoperator catheter digitization error of 1.6 mm. Preliminary analysis of data acquired from four patients indicated a mean registration error of 4.2 mm. Results obtained using the proposed algorithm are clinically acceptable especially considering the complications normally encountered when imaging during lung HDR brachytherapy.

새로운 디지털 인코딩 기법을 적용한 8비트 1GS/s 프랙셔널 폴딩-인터폴레이션 ADC

본 논문에서는 폴딩 구조에 저항열 인터폴레이션 기법을 적용한 1.2V 8b 1GS/s CMOS folding-interpolation A/D 변환기(ADC)에 대해 논한다. 기존 폴딩 ADC가 갖는 경계조건 비대칭 오차를 최소화하기 위해 홀수개의 폴딩 블록과 프랙셔널 폴딩 비율(fractional folding rate)을 사용하는 구조를 제안한다. 또한, 프랙셔널 폴딩기법을 구현하기 위해 덧셈기를 사용하는 새로운 디지털 인코딩기법도 제안한다. 그리고 iterating offset self-calibration 기법과 디지털 오차 보정 회로를 적용하여 소자 부정합과 외부 요인에 의한 노이즈 발생을 최소화하였다. 제안하는 A/D 변환기는 1.2V 0.13um 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 2.1mm<SUP>2</SUP> 유효 칩 면적과(A/D 변환기 core : 1.4mm<SUP>2</SUP>, calibration engine : 0.7mm<SUP>2</SUP>), 350mW의 전력 소모를 나타내었다. 측정결과 변환속도 1GS/s에서 SNDR 46.22dB의 특성을 나타내었다. INL 과 DNL 은 자체보정회로를 통해 모두 1LSB 이내로 측정되었다.

Performance Evaluation of Efficient XOR Structures in Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation nanoelectronic computational architecture that encodes binary information as electronic charge configuration of a cell. It is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. Fundamental unit in building of QCA circuits is a QCA cell. A QCA cell is an elementary building block which can be used to build basic gates and logic devices in QCA architectures. This paper evaluates the performance of various implementations of QCA based XOR gates and proposes various novel layouts with better performance parameters. We presented the various QCA circuit design methodology for XOR gate. These layouts show less number of crossovers and lesser cell count as compared to the conventional layouts already present in the literature. These design topologies have special functions in communication based circuit applications. They are particularly useful in phase detectors in digital circuits, arithmetic operations and error detection & correction circuits. The comparison of various circuit designs is also given. The proposed designs can be effectively used to realize more complex circuits. The simulations in the present work have been carried out using QCADesigner tool.

Webカメラの入力を用いたリアルタイムデータモッシングの表現手法

Art making use of digital noise and errors has been exhibited in recent years. Many of these works have been classified as “glitch” and are forming a new trend in multimedia art. “Datamoshing”, using noise or errors in video imagery, is a technique in the field of glitch art. While one can produce a video that is a unique representation of datamoshing, real-time datamoshing using input from web cameras has not been achieved. Software is proposed for using a web camera to extemporarily datamosh video.

Assessment of Gradient-based Digital Speckle Correlation Measurement Errors

The optical method Digital Speckle Correlation Measurement (DSCM) has been extensively applied due its capability to measure the entire displacement field over a body surface. A formula of displacement measurement errors by the gradient-based DSCM method was derived. The errors were found to explicitly relate to the image grayscale errors consisting of sub-pixel interpolation algorithm errors, image noise, and subset deformation mismatch at each point of the subset. A power-law dependence of the standard deviation of displacement measurement errors on the subset size was established when the subset deformation was rigid body translation and random image noise was dominant and it was confirmed by both the numerical and experimental results. In a gradient-based algorithm the basic assumption is rigid body translation of the interrogated subsets, however, this is in contradiction to the real circumstances where strains exist. Numerical and experimental results also indicated that, subset shape function mismatch was dominant when the order of the assumed subset shape function was lower than that of the actual subset deformation field and the power-law dependence clearly broke down. The power-law relationship further leads to a simple criterion for choosing a suitable subset size, image quality, sub-pixel algorithm, and subset shape function for DSCM.

A New Calibration Method for Digital Power Metering System

Currently in the smart substation, the traceability method of the digital metering system is a sub-component traceability method, which means that the electronic transformer and the digital power meter are calibrated separately. However, the calibrations of the electronic transformer and the digital power meter have been the problem of measuring department, its traceability having been unable to be a good solution. In this situation, this paper proposes a new digital metering system calibration method, and the overall error of the digital metering system can be calibrated. An on-site calibration of digital metering system was carried out on the heihe xigangzi substation. The result showed that this digital metering system error was 1.013%, which is consistent with the theoretical value.

A new two‐step single slope A/D converter for using in CMOS image sensors

SUMMARYThis paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Map-Aided Integrity Monitoring of a Land Vehicle Navigation System

The concept of user-level integrity monitoring has been successfully applied to air transport navigation systems, where the main focus is on the errors associated with the Global Positioning System (GPS)-data-processing chain. Little research effort has been devoted to the study of integrity monitoring for the case of land vehicle navigation systems. The primary difference is that it is also necessary to consider errors associated with a spatial map and a map-matching (MM) process when monitoring the integrity of a land vehicle navigation system. This is because these two components play a vital role in land vehicle navigation. To date, research has focused on either the integrity of raw positioning data obtained from GPS or the integrity of the MM process and digital map errors. In this paper, these sources of error are simultaneously considered. Therefore, the main contribution of this paper is to report the development of a user-level integrity-monitoring system that concurrently takes into account all the potential error sources associated with a navigation system and considers the operational environment to further improve performance. Errors associated with a spatial road map are given special attention. Two knowledge-based fuzzy inference systems were developed to measure the integrity scale. The performance of the integrity method was assessed using field data collected in Nottingham and London, U.K. The results indicate that the integrity method provides valid warnings 98.2% and 99.4% of the time for positioning data in a mixed operational environment in Nottingham and suburban areas of London, respectively.

All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation

In this paper, an all digital push-pull linear voltage regulator is proposed that consists of a digital error detector, a voltage divider, a mode indicator, a pull device, and grouped push devices. The digital regulator is suitable for super- to near-threshold region operation by providing a variable output voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum load current is 100 mA for every output level. The current efficiency is 99.8% with only 164.5 μ A quiescent current on UMC 65-nm standard CMOS technology. A response time constraint is developed to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance and the size of the decoupling capacitor. A time interleaving control technique is then proposed to have a tradeoff between output performance, quiescent current, and the size of decoupling capacitor.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-<TEX>${\mu}m$</TEX> 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 <TEX>$mm^2$</TEX> and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 ㎚ 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-㏈ and SFDR is 62.04-㏈c when the input frequency is 78.15 ㎒ at 500 MS/s conversion rate. The SNDR of the ADC is 7-㏈ higher than the same circuit without the proposed calibration. The effective chip area is 1.55 ㎟, and the power dissipates 300 ㎽ including peripheral circuits, at a 1.2/1.5 V power supply.

Study on Reproduction of Color Information of Digital Image Based on Different Color Gamut

This paper is based on digital image color information reproduction error in a different color gamut,Through the different color gamut mapping method, image processing software Photoshop is used to make experiment and to obtain the corresponding image effect. Using digital presses to print out and use Spectrodensitometer measure the corresponding data.Using Excel software for data processing and analysis, digital image color information of loss situation is obtained in RGB and CMYK color space, It can provide certain basis for control of the color loss.

Research of Detection and Control System for Lunar Dust Effects Simulator

To simluate the effects of lunar dust environment veritably by using lunar dust effects simulator, a detection and control system based on singlechip microcomputer was developed. In this system, peripheral circuits with stepper motor driver, temperature sensor and rotary transformer were used to collect the signals and control the temperature as well as speed. Stepper motor speed up/down curve, digital convolution filter and error compensation were adhibited for improving the system accuracy. The results showed that this method was simple, reliable and had high control accuracy.

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

Inter-tester reliability of non-invasive technique for measurement of innominate motion

Although the complex anatomical orientation and position of the sacroiliac joints (SIJ) has rendered their 3D kinematic evaluation difficult, recent techniques of palpation–digitization of pelvic landmarks using electromagnetic tracking device have been able to accurately and non-invasively quantify the subtle SIJ kinematics. While this technique demonstrates radiographic validity and high test-retest reliability, it is yet to be assessed with regards to inter-tester and trial-to-trial reliability. A single-group repeated measure design using 4 testers was conducted to evaluate the inter-tester and trial-to-trial reliability of palpation–digitization technique for innominate vector length measurements using the Polhemus electromagnetic tracking device. Fourteen young, healthy adults between the ages of 18–40 years participated in the study. The innominate vector length was calculated from 3D co-ordinates of palpated and digitized pelvic landmarks in two test positions of hip. A sensitivity analysis was conducted to determine how palpation–digitization errors for pelvic landmarks impacts on innominate angle calculation. Reliability indexes of Intraclass correlation coefficient (ICC) (≥0.97) and Standard error of measurement (SEM) (≤2.02 mm) demonstrated very high inter-tester and trial-to-trial reliability and accuracy of palpation–digitization technique for innominate vector length measurements, irrespective of the two test positions. A higher consistency of measurements was obtained within-testers as compared to between testers, and sensitivity analysis demonstrated a negligible influence of palpation–digitization errors on the innominate angle measurements. The results support clinical and research utility of this technique for non-invasive kinematic evaluation of SIJ motion for this population. Further research on the use of this palpation–digitization technique in symptomatic population is warranted.