One of the fastest adder architecture among the prevailing adder architectures. Adders are digital logic devices that add binary numbers together. They are commonly used as a component in an Arithmetic Logic Unit which itself is a component in Central Processing Unit. As a result any electronic device that has a Microcontroller or a CPU such as smart thermostats, digital alarm clock, digital wrist watches, and digital bathroom scales etc use adder circuit. In this work, we present an 8 bit hybrid Carry Select Adder architecture. It employs Parallel prefix addition using Kogge stone adder structure, Brent Kung adder structure, Han Carlson Adder structure and Ladner Fischer adder structures. It also employs Binary to Excess 1 code converter along with parallel prefix adders. Affirmation of the suggested design completed using Verilog code and simulated using Xilinx ISE 14.7 and the power, area and delay results were calculated using Cadence software. Comparisons with existing conventional adder architecture certify its better quality. The experimental analysis probes that the recommended hybrid carry select adder results threefold advantages in regards with speed, area and power.
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