The semiconductor industry has been based on Si device scaling for many decades. The motivation for scaling Si is well known, as the reduced dimensions can lead to increased field-effect transistor (FET) device (logic) performance with lower power consumption, thereby enabling a vast array of consumer electronic products. While other materials such as Ge, III-Vs, and 2D materials have threatened to replace Si in FET device channels, it remains at the core of modern digital logic transistors and circuits.Si has been scaled below 10 nm in multi-gate and silicon-on-insulator (SOI) device technologies, but its thickness cannot be reduced indefinitely and larger surface-to-bulk ratios will impact the behaviour of the Si. In general, surface physics cannot be discounted as thickness approaches 5 nm. It is known that effects must be considered at these scales such as carrier surface scattering, dielectric screening, interface states, as well as decreased doping efficiency, increased dopant trapping, and an increase in Si bandgap. If not properly controlled, or at least understood, these factors may inhibit proper semiconductor operation.Damage-free doping processes are desirable as crystal defects or surface roughness can, not only, negatively impact individual transistor device performance, but can also introduce an uncontrolled variability among devices. A conformal process implies access to all surfaces equally in order to, in this case, uniformly and reliably modify the material. Uniformity is necessary as it reduces local resistance variation which again can lead to poor electrical behaviour. As we transition to Gate-All-Around (GAA) device architectures, where all sides of the semiconductor are accessible in theory, having processes that can actually demonstrate access to the bottom surface are becoming increasingly sought after. When dealing with 3D structures the impact of surface effects becomes crucial in determining the active dopant levels. These surface effects lead to problems for dopant incorporation/activation or as gettering points where dopants pile up. Another problem with the greater exposure to the perimeter of the 3D devices is when the doping process etches the available surface, severely damaging or destroying these devices.In this presentation we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion. As Si devices scale, the effect of beamline induced crystal damage compounds as a greater percentage of the device area will consist of damaged crystal. Beamline induced surface damage will become a more prominent issue with increasing surface to volume ratios of Si devices. Sputtering of the Si surface by the ion beam is likely to become a more limiting factor once device pitch becomes scaled limiting the acceptable implantation angles. Limitation of the beamline angles will lead to shadowing of the Si devices, and therefore asymmetrical dopant levels. With the advent of GAA devices, line-of-sight implantation methodologies may be unsuitable for the doping of 3D stacked devices.On the other hand in-diffusion techniques suffer due to a surface barrier that must be overcome in order to enter the Si, while ions can always be implanted beyond the surface into the target. Pioneering solutions may exist in the fields of proximity doping and novel surface passivation techniques. Gas-phase doping has a greater potential than liquid or solid phase processes to dope the increasingly complex 3D geometries of Si devices as liquid coverage can be limited by wetting, and solid sources can be limited when fin and nanowire pitches are scaled.
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Open Access
Feb 1, 2024
Yuqing Mao + 3
