Time-to-digital Converter Research Articles

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS

In this paper, an 800 MS/s 12bit voltage-time hybrid domain ADC is presented. A four-channel split time-to-digital converter (TDC) is proposed in the first-stage sub-TDC, effectively reducing the impact of skew error. A configurable time amplifier (TA) is proposed to pre-configure the discharge voltage, optimizing the conversation rate and power consumption. The hybrid domain ADC verified in a 28-nm CMOS process with a core area of 0.033 mm2, which achieves 65.66 dB SNDR and 72.16 dB SFDR while consuming 7.93 mW from a single 0.9-V supply, resulting in Walden figure-of-merit (FoM) values of 6.34 fJ/conversion-step.

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.

Prototype development of a three-stage, high-precision, low-jitter, wide-range digital delay generator fully utilizing on-chip resources.

This paper introduces the design and implementation of a prototype Digital Delay Generator (DDG) characterized by high precision, low jitter, and a wide delay range, fully realized within a Field Programmable Gate Array (FPGA). The DDG's architecture is based on an innovative combination of an embedded time-to-digital converter (TDC) and Multi-stage Time Interpolation (MTI) delay logic. The paper explores the factors influencing delay jitter during external trigger mode and carefully selects the optimal design approach for each element. The embedded TDC, which undergoes automatic calibration, accurately measures the time difference between the arrival of an external trigger and the FPGA's internal clock signal. When paired with the MTI delay logic, this allows for highly precise control over delay durations. A key aspect of this design is its sole dependence on the FPGA's built-in resources, ensuring simplicity in implementation and adaptability to various applications. Evaluation of the prototype has shown promising results, demonstrating a delay resolution as fine as 20ps and maintaining a low jitter of 105ps peak-to-peak (20ps rms) when operated in the externally triggered mode.

High-Performance Wave Union Time-to-Digital Converter Implementation Based on Routing Path Delays of FPGA

Time-to-digital converters (TDCs) with superior performance are in high demand in application domains like light detection and ranging (LIDAR), nuclear physics, and time interval counters. One of the interesting architectures for field-programmable gate array (FPGA)-based TDCs is the tapped delay line (TDL) approach with carry chains as delay elements. However, the resolution of TDL-TDCs is limited, and linearity is weakened by the ultra-wide bins that correspond to the FPGA’s long routing wires crossing into another clock area. This paper presents wave union TDC using FPGA internal routing wires as delay elements to subdivide ultra-wide bins. The Zynq Evaluation and Development (ZED) board is used to implement and test the wave union types: A (WU-A) and B (WU-B) TDCs. According to experimental data, the WU-A TDC based on an 8 × 128 matrix of counters has a resolution of 5.7 ps, an integral nonlinearity (INL) of 1.1170 LSB (RMS), and a differential nonlinearity of 0.329 LSB (RMS). WU-A TDC improves DNL and INL by 19% and 57%, respectively, over ordinary TDC. The WU-B TDC uses an average of sixteen different time measurements, resulting in an effective resolution of up to 0.356 ps, a DNL of 0.60 LSB (RMS), and an INL of 1.04 LSB (RMS). These characteristics make the TDC suitable for time-of-flight applications such as LIDAR and for other general-purpose scientific instruments.

The prototype of the front-end electronics for STCF muon detector

The muon detector (MUD), serving as the outermost detector of the high-precision spectrometer in STCF, is used to provide muon identification in the presence of a significant pion background. The accuracy of muon identification relies heavily on excellent momentum resolution, which can be determined by their flight trajectory positions. Physical simulations of the measurement precision for reconstructed muons indicate that a spatial resolution of 2 cm is required. In the barrel MUD, a double-ended readout is required to determine the hit position, with a time resolution requirement of approximately 500 ps. To meet the readout requirements of the MUD, a comprehensive scheme for the front-end readout electronics of the STCF MUD is proposed, and a prototype of MUD readout electronics is developed. To validate the final 8-channel application-specific integrated circuit (ASIC) design, an 8-channel time-to-digital converter (TDC) is implemented using a field programmable gate array (FPGA). The results of the electronics tests demonstrate that the average root mean square (RMS) precision ranges from 14 to 16 ps for each channel within a 1∼20 ns time interval. In the joint test with the detector, the system achieves a single-channel RMS precision of 297 ps, with a detection efficiency exceeding 95.5%. All indicators meet project requirements. This validates that the prototype is capable of preliminary evaluation and parameter optimization of the STCF MUD.

A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz.

The analog front end for FastRICH: an ASIC for the LHCb RICH detector upgrade

This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout detectors like Photomultiplier Tubes to be used at the LHC Run 4 and Silicon Photomultipliers candidates for Run 5. The front-end (FE) stage has an input impedance below 50 Ω and an input dynamic range from 5 μA to 5 mA with a power consumption of ∼5 mW/channel. The chip includes a Leading Edge Comparator (LED) and a Constant Fraction Discriminator (CFD) for time pick-off and a Time-to-Digital Converter (TDC) for digitization.

Current status and applications of time-to-digital converters

Time-to-Digital Converter (TDC) is widely used to realize time interval measurement. The high-precision time measurement technique has important applications in the fields of laser ranging, particle identification, and radioactive nuclear medicine engineering. Based on the existing literature research and data, this paper studies the application areas of TDC in the present development and analyzes the future prospects of TDC applications. The research results showed that: TDC, based on signal screening, realizes time interval measurement as the ultimate purpose of building the system and, at the same time, completes the function of multi-pulse time interval measurement, which can meet the needs of more diversified measurements in the experiments. In the circuit structure, it can identify the feedback output in the all-digital phase-locked loop (ADPLL) and the reference clock phase and frequency information between the feedback output and the reference clock in an ADPLL. It is also promising for use in other areas of high-precision time measurement and processing of circuit signals.

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient

This work suggests an all-digital temperature sensor with a high sampling rate that is based on a time-to-digital converter (TDC). Two on-chip voltage-controlled oscillators (VCOs) are used in the design of the sensor core, which senses temperatures between [Formula: see text]C and 200[Formula: see text]C. For digital code conversion, the outputs of the VCO are fed into two asynchronous counters. In both low- and high- resolution modes, the error following two-point calibration is observed between [Formula: see text]C and [Formula: see text]C. The sensor’s ability to function in both high- and low-resolution modes based on conversion time is an important feature. At a sampling frequency of 0.19[Formula: see text]MHz, the maximum resolution achieved is 0.18[Formula: see text]C. Additionally, the sensor has control logic built in to turn off the sensing as soon as the conversion is complete. At 90-nm process, 1.1[Formula: see text]V supply voltage and 27[Formula: see text]C, the proposed sensor occupies [Formula: see text] and consumes [Formula: see text].

A high-pass shaped LMS algorithm based predistortion technique for fractional-[formula omitted] BB-DPLLs

In this paper, we prove that rather than the second-order ΔΣ modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional-N Bang-Bang digital phase-locked-loops (BB-DPLLs). We also propose a novel technique that addresses the limit-cycle issue happening in near-integer channels of the conventional BB-DPLLs. With the first-order DSM-based novel technique, simulation results show that the worst fractional spurs are below −83 dBc at 12 kHz offset frequency assuming the DTC’s integral nonlinearity error is as large as 5 least-significant-bits.

Ring Oscillator Based True Random Number Generator

Abstract: A true random number generator (TRNG), also known as a hardware random number generator (HRNG), does not use a computer algorithm. Instead, it uses an external unpredictable physical variable such as stochastic models to generate random numbers. Here it gathers data from random electronic signals. Then, the data is converted into digital form and any patterns registered are removed to make it random. This data is used to create random numbers. It is mainly used in Cryptographic Security, authentication, secure communications, e-commerce transactions, Digital Signatures etc. In Existing Method, LFSR based TRNGs generate pseudo random numbers. They produce sequences of bits that appear random but are deterministic and repeat after a certain number of cycles known as the period. They are easy to predict and are not suitable for high security applications. This project aim is to overcome such circumstances, we use TERO(Three Edge Ring Oscillator) based TRNG. Three edges are simultaneously injected by each inverting NAND stage with enable signal Run. These edges will have an identical mean period since they propagate through the same stages. The TERO generates an oscillating signal with a frequency determined by the delay of inverters. TDC (Time to Digital Converter) is used to precisely measure the time intervals between the rising edges of TEROs output signal. Then, it converts time intervals into digital values, effectively generating truly random numbers. Power consumption depends on factors like operating frequency and load capacitance. The Software used is Xilinx Vivado/Xilinx ISE Tools. Here the Proposed Method exquisitely balances Low design effort and resource consumption with high throughput and high randomness.

On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ

This work presents a fully integrated, self-clocked temperature-to-digital converter-based smart temperature sensor for thermal monitoring of SoC for self-heating problem. The design utilizes the channel length modulation coefficient λ with MOSFET sensing followed by a time-to-digital converter (TDC). The proposed method considers the ratio of saturation currents of two nMOSFETs with constant gate voltages but different gate lengths. At a CMOS process of 90-nm and supply voltage of 1.1 V, the sensor occupies a small area of 0.047 mm2. The sensor further attains a resolution of 0.036OC over a temperature range of −40OC to 100OC and limits the inaccuracy between −0.79OC and 0.78OC after two-point calibration.

A capacitive mismatch calibration method for SAR ADCs based on TDC

AbstractThe capacitance mismatch problem limits the accuracy improvement of high‐precision SAR ADCs (Successive Approximation Register Analog‐to‐Digital Converters). To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time‐to‐Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13‐bit SAR ADC can be completely eliminated, and the effective number of bits (ENOB) approach the ideal value of 13.18 bits. Additionally, the analog component of this scheme utilizes four inverter chains, two D flip‐flops, and four counters, without requiring a large area for auxiliary calibration capacitors.

Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70 μm pixel pitch

This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32 × 32 pixel matrix at 70 μm pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30 %. A sub-100 ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3 MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4 Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation delays across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.

A 6-9 GHz 1.28 Gbps 76 mW Amplitude and Synchronized Time Shift Keying IR-UWB CMOS Transceiver for Brain Computer Interfaces.

This paper proposes a low-power, high-speed impulse radio-ultra-wideband (IR-UWB) transceiver for brain computer interfaces (BCIs) using amplitude and synchronized time shift keying technique (ASTSK). The proposed IR-UWB transmitter (Tx) generates two pulses (sync pulse and data pulse) per symbol rate. The time difference between two pulses is used for synchronized time shift keying and the amplitude of the two pulses is used for amplitude shift keying. The receiver (Rx) demodulates the time difference with a low power time-to-digital converter (TDC) and peak detector (PD) based amplitude demodulation is suggested to relax analog-to-digital converter (ADC) burden for low power receiver. Especially the Tx-based synchronized operation eliminates the need for complex clock circuitry such as phase-lock loop (PLL) and reference crystal oscillator. Therefore, it can achieve low power and high-speed operation. The prototype, fabricated in 65 nm CMOS, has a frequency range of 6-9 GHz, communication speed of 1.28 Gbps, and power consumption of 18 mW (Tx) and 58 mW (Rx). This work is a fully integrated RF transceiver adapted for high-order modulation and designed to include the receiver.

An Ultrasonic Transceiver for Non-Invasive Intracranial Pressure Sensing.

This paper presents a 9-mW ultrasonic through-transmission transceiver (TRX) for portable, non-invasive intracranial pressure (ICP) sensing. It employs two ultrasound transducers placed at the temporal bone windows to measure changes in the ultrasonic time-of-flight (ToF), based on which the skull expansion and the corresponding ICP waveform are derived. Key components include a high-efficiency Class-DE power amplifier (PA) with 95% efficiency and an output swing of 15.8 VPP, along with a successive approximation register (SAR) delay-locked loop (DLL)-based time-to-digital converter (TDC) with 29.8 ps resolution and 122 ns range. Other than electrical characterization, the sensor is validated through two demonstrations using a water tank setup and a human head phantom setup, respectively. It demonstrates a high correlation of R2 = 0.93 with a medical-grade invasive ICP sensor. The proposed system offers high accuracy, low power consumption, and reliable performance, making it a promising solution for real-time, portable, non-invasive ICP monitoring in various clinical settings.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

LinoSPAD2: an FPGA-based, hardware-reconfigurable 512×1 single-photon camera system.

We report on LinoSPAD2, a single-photon camera system, comprising a 512×1 single-photon avalanche diode (SPAD) front-end and one or two FPGA-based back-ends. Digital signals generated by the SPADs are processed by the FPGA in real time, whereas the FPGA offers full reconfigurability at a very high level of granularity both in time and space domains. The LinoSPAD2 camera system can process 512 SPADs simultaneously through 256 channels, duplicated on each FPGA-based back-end, with a bank of 64 time-to-digital converters (TDCs) operating at 133 MSa/s, whereas each TDC has a time resolution of 20 ps (LSB). To the best of our knowledge, LinoSPAD2 is the first fully reconfigurable SPAD camera system of large format. The SPAD front-end features a pitch of 26.2 μm, a native fill factor of 25.1%, and a microlens array achieving 2.3× concentration factor. At room temperature, the median dark count rate (DCR) is 80 cps at 7 V excess bias, the peak photon detection probability (PDP) is 53% at 520 nm wavelength, and the single-photon timing resolution (SPTR) is 50 ps FWHM. The instrument response function (IRF) is around 100 ps FWHM at system level. The LinoSPAD2 camera system is suitable for numerous applications, including LiDAR imaging, heralded spectroscopy, compressive Raman sensing, and other computational imaging techniques.

16-channel SiPM high-frequency readout with time-over-threshold discrimination for ultrafast time-of-flight applications

BackgroundOver the past five years, ultrafast high-frequency (HF) readout concepts have advanced the timing performance of silicon photomultipliers (SiPMs). The shown impact in time-of-flight (TOF) techniques can further push the limits in light detection and ranging (LiDAR), time-of-flight positron-emission tomography (TOF-PET), time-of-flight computed tomography (TOF-CT) or high-energy physics (HEP). However, upscaling these electronics to a system-applicable, multi-channel readout, has remained a challenging task, posed by the use of discrete components and a high power consumption. To this day, there are no means to exploit the high TOF resolution of these electronics on system scale or to measure the actual timing performance limits of a full detector block.MethodsIn this work, we present a 16-channel HF readout board, including leading-edge discrimination and a linearized time-over-threshold (TOT) method, which is fully compatible with a high-precision time-to-digital converters (TDCs), such as the picoTDC developed at CERN. The discrete implementation allows ideal adaptation of this readout to a broad range of detection tasks. As a first step, the functionality of the circuit has been tested using the TOFPET2 ASIC as back-end electronics to emulate the TDC, also in view of its properties as a highly scalable data acquisition solution.ResultsThe produced board is able to mitigate influences of baseline shifts in the TOFPET2 front end, which has been shown in experiments with a pulsed laser, increasing the achievable intrinsic coincidence timing resolution (CTR) of the TOFPET2 readout electronics from 70 ps (FWHM) to 62 ps (FWHM). Single-channel coincidence experiments including a γ\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\gamma$$\\end{document}-source, 2×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}2×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}3 mm3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$^{3}$$\\end{document} LYSO:Ce,Ca crystals and Broadcom NUV-MT SiPMs resulted in a CTR of 118 ps (FWHM). For a 4×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}4 matrix of 3.88×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}3.88×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}19 mm3\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$^{3}$$\\end{document} LYSO:Ce,Ca crystals one-to-one coupled to a 4×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ imes$$\\end{document}4 array of Broadcom NUV-MT SiPMs, an average CTR of 223 ps (FWHM) was obtained.ConclusionThe implemented 16-channel HF electronics are fully functionall and have a negligible influence on the timing performance of the back-end electronics used, here the TOFPET2 ASIC. The ongoing integration of the picoTDC with the 16-channel HF board is expected to further set the path toward sub-100 ps TOF-PET and sub-30ps TOF resolution for single-photon detection.