Abstract
In this paper, we prove that rather than the second-order ΔΣ modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional-N Bang-Bang digital phase-locked-loops (BB-DPLLs). We also propose a novel technique that addresses the limit-cycle issue happening in near-integer channels of the conventional BB-DPLLs. With the first-order DSM-based novel technique, simulation results show that the worst fractional spurs are below −83 dBc at 12 kHz offset frequency assuming the DTC’s integral nonlinearity error is as large as 5 least-significant-bits.
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