Analog-to-digital Research Articles

Comparative Study and Simulation of ADC Using MATLAB/SIMULINK

Digital systems play an important role in science and engineering field due to high noise immunity,high accuracy and required less space for data storage. And since all physical quantities are available in analog form so we need device which convert these quantities into digital one this device is called analog to digital converter (ADC).In this paper we present and simulate model for ADC using MATLAB/SIMULINK .

Rapid phase current sampling in a permanent magnet synchronous motor servo system utilizing flexible memory controller bus

Background The permanent magnet synchronous motor (PMSM) servo system, integral to robots and other high-precision motion control applications, has its performance directly influenced by the current loop in the PMSM servo system. Though the theoretical adjustment time of the current loop can approach the electrical time constant of PMSM in order of magnitude, constraints such as control frequency make the adjustment time significantly larger than this theoretical limit. Methods This paper introduces a PMSM servo system using a flexible memory controller (FMC) bus for rapid phase current sampling. It leverages an independent current sampling module, equipped with an external analog-to-digital (AD) conversion chip for precise sampling of the output phase current of the PMSM. The sampling precision is 16-bit with a range of 0-3V. The sampled signal is preprocessed by a field-programmable gate array (FPGA), with the phase current data finally transmitted to the primary control chip through the FMC bus. Results By implementing this rapid current sampling architecture, we have successfully reduced the current sampling time by 95.4% while maintaining sampling accuracy. This scheme also substantially shortens the microcontroller unit’s (MCU) interrupt response time, potentially enhancing the current loop's control frequency, ultimately increasing the current loop bandwidth to 20kHz. Conclusions In conclusion, the proposed PMSM servo system with rapid current sampling significantly enhances the performance of the current loop. This advancement in sampling efficiency and control frequency offers substantial improvements for high-precision motion control applications, making it a valuable contribution to the field.

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

Multi-channel photonic sampled ADC with hybrid deep-learning for distortion recovery

Analog-to-digital converter (ADC) is indispensable components in modern information systems, and photonic technologies have emerged as promising avenues for overcoming bottlenecks in ADC performance. This paper introduces a novel approach: a photonic sampled ADC integrated with a neural network that combines Convolutional Neural Networks (CNNs) and Transformers for data recovery. The proposed system utilizes a multi-wavelength optical sampling pulse train interleaved in the time domain through fiber dispersion. Sampled signals are quantified in parallel channels by electronic ADC (EADC). Through supervised training, the hybrid deep neural network extracts both local and global features of photonic system defects, enabling the recovery of distorted data. Experimental validation showcases the effectiveness of this architecture, achieving successful reconstruction of radio frequency (RF) signals at a sampling rate of 12 Giga-samples per second (Gs/s) with an effective number of bits (ENOB) of 7.13. The results underscore the potential of the proposed architecture in achieving high conversion accuracy in multi-channel photonic sampled ADCs.

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry

This paper presents a signal-chain friendly 12-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) in 40nm CMOS, which is optimized to achieve a 68.5 dB-SNDR, 100-MS/s sample rate with 54.5% of maximum available input range. The implemented ADC employs an improved clock booster and latch-register to achieve high on-conductance of nmos switches and low-leakage data storage. It also explores an adaptive non-overlapping complementary clock generator and a dedicated VCM buffer to accommodate process, voltage, and temperature (PVT) conditions. The relative variation of non-overlapping time is reduced by 50% compared to the conventional method, and the signal-to-distortion ratio (SDR) of residue amplification is improved by 8dB . Moreover, on-chip bit weight calibration is implemented to address the gain error brought by capacitor mismatch and inner-stage gain error. The prototype ADC is simulated under 5 corners, −40 to 125°C, and 1.1V±2.5%. For a Nyquist input, the simulated SNDR under typical corner is 68.5dB , which can remain over 66dB under PVT conditions. The achieved Walden Figure of Merit (FoM) is 12.4-fJ/conv.-step.

A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

Mitigating noise in digital and digital–analog quantum computation

Noisy Intermediate-Scale Quantum (NISQ) devices lack error correction, limiting scalability for quantum algorithms. In this context, digital-analog quantum computing (DAQC) offers a more resilient alternative quantum computing paradigm that outperforms digital quantum computation by combining the flexibility of single-qubit gates with the robustness of analog simulations. This work explores the impact of noise on both digital and DAQC paradigms and demonstrates DAQC’s effectiveness in error mitigation. We compare the quantum Fourier transform and quantum phase estimation algorithms under a wide range of single and two-qubit noise sources in superconducting processors. DAQC consistently surpasses digital approaches in fidelity, particularly as processor size increases. Moreover, zero-noise extrapolation further enhances DAQC by mitigating decoherence and intrinsic errors, achieving fidelities above 0.95 for 8 qubits, and reducing computation errors to the order of 10−3. These results establish DAQC as a viable alternative for quantum computing in the NISQ era.

Religious ideologies of minimal computing: negotiating digital technology in religious nationalist education

ABSTRACT Using resistance to digital technologies in religious nationalist public high schools in Israel as a frame for discussing minimal computing, this paper explores how socio-religious ideologies foster minimal technological practices. Based on interviews with administrators, homeroom teachers, and religious and secular content teachers from three schools near an urban center, the study explores how multiple mandates to provide religious, nationalist, and modern education shape teachers’ educational approaches to digital technologies. The paper argues that an approach that segregates technologies to secular domains disentangles digital devices from religious subjectivity; one that allocates time for ‘profane’ digital technologies creates discontinuity between digital practices and religious educational aims; and one that integrates technologies into religious practice fosters a symbiotic digital–analog religiosity. By highlighting the role of religious ideology in shaping limited technological approaches, the paper explores how constraints on teachers’ practices stem not only from resource-driven limitations but from minimal technological will.

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.

Twice‐input variable‐resolution single‐side switching scheme without reset energy for SAR ADC

AbstractA twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications.

Unlimited sampling beyond modulo

Analog-to-digital converters (ADCs) act as a bridge between the analog and digital domains. Two important attributes of any ADC are sampling rate and its dynamic range. For bandlimited signals, the sampling should be above the Nyquist rate. It is also desired that the signals' dynamic range should be within that of the ADC's; otherwise, the signal will be clipped. Nonlinear operators such as modulo or companding can be used prior to sampling to avoid clipping. To recover the true signal from the samples of the nonlinear operator, either high sampling rates are required, or strict constraints on the nonlinear operations are imposed, both of which are not desirable in practice. In this paper, we propose a generalized flexible nonlinear operator which is sampling efficient. Moreover, by carefully choosing its parameters, clipping, modulo, and companding can be seen as special cases of it. We show that bandlimited signals are uniquely identified from the nonlinear samples of the proposed operator when sampled above the Nyquist rate. Furthermore, we propose a robust algorithm to recover the true signal from the nonlinear samples. Compared to the existing methods, our approach has a lower mean-squared error for a given sampling rate, noise level, and dynamic range. Our results lead to less constrained hardware design to address the dynamic range issues while operating at the lowest rate possible.

Measurement of thermophysical parameters of artificial skin

Computer methods for process research and methods for processing the measurement results of the parameters of these processes are widely used in biology and medicine. Therefore, the problem of automation of biophysical measurements and computer processing of the results of such experiments is relevant. In the treatment of wounds and burns with a large surface area of tissue damage, medicine has to resort to artificial skin. A procedure for studying thermal processes in artificial skin and measuring its thermophysical parameters was developed. The measurement process was described. The thermophysical parameters of the artificial skin samples used in medicine for the treatment of wounds and burns were determined. The samples of the artificial skin used were made in Ukraine. Each sample was made from six layers of skin. To control the temperature distribution in the sample between the skin adjacent layers and on the surface of the sample, thermocouples were placed. The surface of the sample was heated with an incandescent lamp. The thermocouple signals were sent to an analog-to-digital converter (ADC), amplified, and digitally transmitted to a computer. Processing was carried out using the ADC software and the MATHCAD program. A mathematical model was obtained. For this purpose, a differential equation describing thermal processes in the sample was solved. The found temperature distribution function and its changes over time are in a good agreement with experimental data. The analysis of the function allows finding the thermal conductivity coefficient of artificial skin, its volume heat capacity, thermal diffusivity coefficient, and heat exchange coefficient with the external environment. The proposed method of measuring and processing experimental data makes it possible to detect main thermophysical parameters of artificial skin. Based on these results, a theoretical model was obtained that well describes the course of thermal processes in artificial skin, which makes it possible to predict the course of these processes. Such method is based on heating the skin with optical radiation. The thermal conductivity and thermal diffusivity of artificial skin are significantly less than such parameters of human skin, which should be considered when using it.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

Direction of Arrival Estimation Based on DNN and CNN

The accuracy of Direction of Arrival (DOA) estimation primarily depends on the precision of the data. When the receiver uses a low-precision analog-to-digital converter (ADC), traditional DOA estimation algorithms exhibit poor accuracy. To face the challenge of multi-target DOA estimation in scenarios with low-precision ADC quantized sampling, this paper proposes a novel DOA estimation algorithm for quantized signals based on classification problems. A deep learning network was constructed using Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs), divided into the quantized signal recovery framework and the DOA estimation framework. The DNN network is utilized to recover signals that have undergone low-precision quantization, while the CNN network addresses the classification problem to estimate the DOA from received data with an unknown number of signal sources. A comprehensive analysis of the impact of signal-to-noise ratio (SNR), the number of array elements, and the number of quantization bits on the proposed algorithm was conducted. Simulation results indicate that the proposed algorithm exhibits superior DOA estimation performance in low-precision scenarios, characterized by reduced computational complexity, thereby facilitating real-time DOA estimation.

A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications.

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain-machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm2. Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW.

Pre-compensating digital-to-analog converter impairments with an LSTM neural network

The performance of high-speed coherent communication heavily depends on digital-to-analog converters (DACs) when they operate within bandlimited and nonlinear regimes. We examine neural network (NN) based digital pre-distortion (DPD) methods to compensate the memory effects that are intertwined with the nonlinear response of the DAC. Using a long short-term memory (LSTM) NN architecture, we examine 8-level amplitude shift keying (ASK-8) at 64 Gbaud. We demonstrate experimental improvements of 1.6 dB and 2 dB in signal-to-noise ratio (SNR) compared to the Volterra and linear solutions, respectively.

End-to-end learning of joint noise shaping and probabilistic shaping for OAM mode division multiplexing transmission.

Intensity modulation direct detection (IM/DD) orbital angular momentum (OAM) mode division multiplexing (MDM) technology can greatly expand the capacity of a communication system, which is a promising solution for the next generation of high-speed passive optical networks (PONs). However, there are serious obstacles such as mode coupling, device nonlinear impairment, and quantization noise in an IM/DD OAM-MDM system with a low-resolution digital-to-analog converter (DAC). In this Letter, we propose a novel, to the best of our knowledge, end-to-end (E2E) learning scheme based on a double residual feature decoupling network (DRFDnet) emulator with joint probabilistic shaping (PS) and noise shaping (NS) for the OAM-MDM IM/DD transmission. Our DRFDnet emulator can accurately build a complex nonlinear model of an OAM-MDM system by separating the signal impairments into linear and nonlinear. Meanwhile, a DRFDnet-based E2E scheme for joint PS and NS is presented with the aim of compensating the signal impairment for the OAM-MDM IM/DD system. An experiment is carried out on a 200 Gbit/s PON system based on the OAM-MDM IM/DD transmission. The experimental results demonstrate that the proposed DRFDnet-based joint PS and NS scheme is a promising solution to effectively mitigate nonlinear distortions and outperforms the CGAN-based joint PS and NS scheme and traditional joint PS and NS scheme with receiver sensitivity improvements of 1.2 dBm and 2.5 dBm under hard-decision forward error correction (HD-FEC) thresholds, respectively. Our experimental results demonstrate that the proposed DRFDnet emulator-based E2E learning scheme is a viable candidate for future PON.

Impacts of sampling on the artificial noise-assisted terahertz secure communication systems

In this paper, we investigate an artificial noise (AN)-assisted terahertz (THz) secure communication system. Different from previous studies, we consider a non-ideal analog-to-digital converter (ADC) in the AN-THz system. Specifically, both synchronization noise and quantization noise in ADC are investigated. The normalized distortion matric is employed to calculate synchronization noise power and the Bellman’s theory is introduced for quantization noise power. Under the constrain of limited ADC power, the secrecy performance presents a ‘U-shaped’ curve versus the sampling rate and therefore the optimal sampling rate is derived. Moreover, we validate our theoretical model in the experiment, and our experimental results in 102 GHz show the synchronization noise power varies with the square of timing error, and the quantization noise power is affected by the total data length, which agree well with the model predictions.

Self-measurement and calibration of amplitude-frequency response for coherent optical transmitters with limited DAC resolution

Precise measurement and calibration of the amplitude-frequency response (AFR) of coherent optical transmitters (Tx) are paramount for generating high-quality signals, especially when the transmitter has insufficient bandwidth. The previously proposed self-measurement and calibration (SMC) method based on multi-tone signals (MTS) is cost-effective, fast, and convenient. However, this method exhibits a compromised AFR measurement precision in high-frequency regions, especially when the digital-to-analog converters (DAC) of the Tx have a limited resolution. To solve this problem, we optimize the amplitudes and phases of the MTS by pre-emphasis and the sequential quadratic programming (SQP) algorithm to improve the accuracy in the high-frequency region. Numerical simulations show a notable reduction in AFR measurement error, from about 4 dB to 0.8 dB, when employing a DAC with a four-bit resolution. Additionally, experiments utilizing a 22 GHz 3-dB bandwidth transmitter to generate 61 GBaud dual-polarization 16QAM signals demonstrate a 60% BER reduction. The proposed SMC method is attractive for high-baud rate systems employing Tx with limited bandwidth and DAC resolution.