Digital Signal Processing Systems Research Articles

Test and evaluation of radar systems operating in the modern electromagnetic spectrum

AbstractModern radar systems are critical infrastructure in defence and civilian applications. In the defence domain, modern radars operate in a highly contested, congested, and constrained electromagnetic environment. In the context of operating in this challenging environment, the challenges across the system life cycle are examined in testing modern radar systems which are characterised by advanced features, such as multi‐function capability, advanced digital signal processing, high resolution, wideband, and frequency agile systems that incorporate phase array and active electronically scanned array capabilities. The challenges and key objectives in testing these sophisticated modern radar systems are highlighted, as well as the enabling technologies that can support Test & Evaluation of such systems. An architecture for Hardware‐in‐the‐Loop testing, which leverages modular and flexible commercial‐of‐the‐shelf hardware, is proposed together with an application software that allows the testing of radar with a radar target generator.

Low Power Multiplier Using Approximate Adder for Error Tolerant Applications

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso.

A Unified Hardware Design for Multiplication, Division, and Square Roots Using Binary Logarithms

Multiplication, division, and square root operations introduce significant challenges in digital signal processing (DSP) systems, traditionally requiring multiple operations that increase execution time and hardware complexity. This study presents a novel approach that leverages binary logarithms to perform these operations using only addition, subtraction, and shifts, enabling a unified hardware implementation—a marked departure from conventional methods that handle these operations separately. The proposed design, involving logarithm and antilogarithm calculations, exhibits an algebraically symmetrical pattern that further optimizes the processing flow. Additionally, this study introduces innovative log-domain correction terms specifically designed to minimize computation errors—a critical improvement over existing methods that often struggle with precision. Compared to standard hardware implementations, the proposed design significantly reduces hardware resource utilization and power consumption while maintaining high operational frequency.

Design of Energy Efficient Arithmetic VLSI Circuits

Advanced electronics have become an integral part of human lives, from Smartphones in our pockets to the modern vehicles on the road and to the satellites that orbit the earth. Power consumption has become a major constraint in these applications, often employing data- intensive digital signal processing systems and architectures. While enormous transistor density at the nanoscale has been increased in the Very Large-Scale Integration (VLSI) multicore era comparable to Moore's law, improving the performance of computing systems has become extremely difficult. Sustaining technological advancements for such energy-constrained devices has paved the way for new areas in research. “Approximate Computing (AC)” has become one of the most promising paradigms, a field that has gainedsignificant attention in the quest for energy efficiency in recent years. AC algorithms are numerically approximate rather than accurate. Inherent error resilience is the primary source of motivation behind AC. Recent research demonstrates that error resilience is pervasive in cyber search, deep learning, multimedia, recognition and data mining. Arithmetic units are the fundamental building blocks in most of the data dominated applications at the micro- architectural level of abstraction. AC is optimal for power and area efficient arithmetic circuits.

Design and implementation of a scalable correlator based on ROACH2 + GPU cluster for tianlai 96-dual-polarization antenna array

The digital correlator is one of the most crucial data processing components of a radio telescope array. With the scale of radio interferometeric array growing, many efforts have been devoted to developing a cost-effective and scalable correlator in the field of radio astronomy. In this paper, a 192-input digital correlator with six CASPER ROACH2 boards and seven GPU servers has been deployed as the digital signal processing system for Tianlai cylinder pathfinder located in Hongliuxia observatory. The correlator consists of 192 input signals (96 dual-polarization), 125-MHz bandwidth, and full-Stokes output. The correlator inherits the advantages of the CASPER system, for example, low cost, high performance, modular scalability, and a heterogeneous computing architecture. With a rapidly deployable ROACH2 digital sampling system, a commercially expandable 10 Gigabit switching network system, and a flexible upgradable GPU computing system, the correlator forms a low-cost and easily-upgradable system, poised to support scalable large-scale interferometeric array in the future.

Development and research of filter models communication and control systems configured for the required set of parameters

Problem statement. A digital filter refers to a hardware or software implementation of a mathematical algorithm that converts a digital signal in a certain way. The classification of digital filters is usually based on the functional characteristics of digital filtering algorithms. Digital filters may have parameters that cannot be implemented in analog filters, do not require periodic monitoring and calibration, and one filter can process several input channels or signals, while the accuracy is limited only by the bit depth used. The implementation of digital signal processing units using programmable logic integrated circuits (FPGAs) will significantly simplify hardware costs and make the most effective use of these digital filter capabilities. Goal. Conducting research in the field of digital signal processing in order to obtain fundamentally new software and hardware architectures, developing an RTL model of a complex functional block (SF block) of a digital signal processing system, its verification both at the logical and physical level. Results. In the course of the scientific research, a software and hardware model of the filter was developed to adjust the parameters during operation, taking into account their architectural advantages and disadvantages. In order to verify and confirm the adequacy of the methodology developed in the course of the study, an SF model was created-a digital signal processing unit. This model has been implemented and physically verified on the basis of a debugging board using FPGAs. Practical significance. The technique presented in this paper will allow the development of software and hardware devices for digital signal processing, with the possibility of their configuration at the software level for the required set of processing parameters, which in turn will significantly save resources spent on development.

Automated design of embedded digital signal processing systems on SOC platform

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Implementation of a Reverse Carry Propagate Adder Based On Efficient VLSI for Hardware Security and Area Consumption

The various techniques inbuilt in the VLSI (Very Large Scale Integration) designing is originated from the basis of adder circuits. When these adder circuits are processed in the higher digital signal processing systems, the adders have to exhibit high performance, good efficiency with reduced cost and area of implementation. The major objective of designing the VLSI design is minimizing the complexity and to perform the operations more effectively. Whereas in some other methods, the logic circuit designing is made larger in order to achieve higher efficiency. This in turn, results in the reduction of hardware security and makes the computation more complex. This paper utilizes the RCPA adder logic to reduce the area for the implementation and enhancing the hardware security. By implementing RCPA adder circuit, the carry propagates in the opposite direction from the most significant bit to the least significant bit. The usage of shift accumulator improves the speed of process and reduces the area required. By implementing the reverse propagation of the carry in the adder circuit, computation time is optimized and the implementation is made efficient with the reduction in the delay.

Recovery of Discrete-Time Signal Based on the Moving Average Model and Estimation of the Samples Correlation in Forward and Reverse Forecasting

The article discusses the development of mathematical support for the recovery of the values of discrete-time sequence samples obtained as a result of uniform sampling of a continuous signal. The recovery problem of discrete-time sequence samples is solved for a signal that can be considered stationary or stationary at least in a broad sense (quasi-stationary). The development of mathematical support for the recovery of the values of signal samples was carried out on the basis of constructing a moving average model and estimating the correlation of signal samples over time with forward and reverse forecasting. Estimates of the signal correlation function necessary to recover sample sections with lost values are calculated from samples with known values. Correlation function estimates can be calculated regardless of the location of the recovery area when the condition of stationarity of the signal is met. The obtained estimates of the correlation function samples can be used for both forward and reverse forecasting. Moreover, even if it is necessary to recover several problem sections, it is enough to calculate only once the sample of correlation function estimates necessary for their restoration. The resulting mathematical solution to the problem became the basis for the development of algorithmic support. Test tests and functional checks of the algorithmic support were carried out on the basis of simulation using a signal model representing an additive sum of harmonic components with random initial phases. The simulation results showed that the calculation of estimates of the lost sample values is carried out with a fairly low error, both in forward and reverse forecasting, as well as when they are used together. In practice, the choice of a sequence recovery algorithm based on forward or reverse forecasting will be determined based on the actual conditions of its processing. In particular, if previous samples with known values are not enough to carry out forward forecasting, then the reverse forecasting procedure is implemented and vice versa. The developed algorithmic support can be implemented in the form of metrologically significant software for digital signal processing systems.

A review in advanced digital signal processing systems

Digital Signal Processing (DSP) is a powerful technology that helps in making sense of various signals, like sounds and images, using computers. This review paper explains the meaning of DSP, shows how it works to process and enhance signals. It explores the wide range of signal processing methods, categorizing them from basic noise reduction to advanced machine learning algorithms, and how they are used today to improve the quality of audio, images, medical data, and other control systems. The paper further examines into signal processing techniques, providing a comprehensive understanding of the diverse methodologies employed in DSP applications. Additionally, it addresses not only the advancements but also the drawbacks associated with advanced DSP systems, offering insightful recommendations for overcoming challenges and optimizing performance. This review also includes categories of DSP methods, providing a structured overview of the different approaches within the field. It offers a clear and concise understanding of DSP, its practical uses, and its exciting potential in the digital age

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Design and Implementation of FIR Filters for Biomedical Applications

Abstract: Digital signal processing (DSP) greatly facilitates the continuous capture, monitoring, processing, and analysis of signals in real-world applications, particularly in biomedical or wearable devices. Within DSP systems, the design of Finite Impulse Response (FIR) filters is pivotal. In scenarios demanding intricate calculations and high precision, higher-order filters are employed. Multipliers are crucial components in filter design, consuming significant chip space and introducing extra computation overhead. Designers strive to optimize multipliers to enhance performance. In this project we are going to design pipelined based FIR filter by applying pipelining concept to the FIR filter and following the previous implementations such as the FIR filter with high accuracy compared to existing method. The proposed system architectures are known to be efficient for real signal processing, offering advantages over conventional based designs. The proposed design is anticipated to yield benefits in terms of area, power consumption, and timing performance. The synthesis and simulation of the existing and proposed designs are implemented using Cadence Virtuoso.

Design Wallace Tree Multiplier Using Reversible Gates

Abstract: Multipliers are essential components in digital circuit design. They have wide spread applications in digital signal processing and communication systems. Circuit designers in VLSI design seek compact, small scale circuits with low power consumption and minimal delay. The Wallace tree multiplier is an advanced version of tree based multipliers. Numerous algorithms have been developed to create the fastest multipliers, and the Wallace tree multiplier is one such example. It utilizes reversible compressors, full adders, and half adders. The results demonstrate that the Wallace tree multiplier using reversible gates outperforms traditional multipliers in terms of power dissipation and delay, with values of 0.027W and 29.327nS re­spectively.

Discrete linear canonical shearlet transform

In this paper, we introduce the continuous and discrete version of the linear canonical shearlet transform (LCST). The authors begin with the definition of the LCST and then establish a relationship between the linear canonical transform (LCT) and the LCST. Next, the paper derives several basic properties like Parseval’s Formula, inversion formula, and the characterization of the transform’s range. In addition to the continuous version of the transform, the authors also present a discrete version of the LCST. This discrete version allows for practical implementation and efficient computation of the transform in digital signal processing systems. Lastly, the paper establishes a frame condition for the discrete LCST, which thereby helps in establishing the reconstruction formula for the discrete LCST. The paper ends with a conclusion.

Harmonizing Innovation: A Journey through the History of Computational Music

The history of computational music traces a fascinating journey of innovation and creativity, intertwining disciplines such as computer science, mathematics, music theory, and psychology. From its inception in the mid-20th century to its current state of sophistication, computational music has evolved into a multifaceted field encompassing algorithmic composition, digital signal processing, machine learning, and interactive music systems. Pioneering works such as Roads' "The Computer Music Tutorial" and Biles' "GenJam" exemplify the early endeavors in digital sound synthesis and algorithmic composition. The roots of computational music extend back to the 1950s and 1960s with the pioneering efforts of Max Mathews, John Chowning, and Lejaren Hiller, laying the groundwork for future advancements. Technological breakthroughs in the 1970s and 1980s, including the advent of digital audio workstations and FM synthesis, further propelled the field forward. The 1990s and 2000s witnessed democratization and accessibility with the rise of affordable software tools and online collaboration platforms. Today, computational music continues to evolve with the emergence of deep learning and generative AI techniques, albeit accompanied by ethical considerations regarding copyright ownership and algorithmic bias. In conclusion, the history of computational music underscores the transformative power of technology in shaping musical expression and invites us to explore new frontiers where creativity knows no bounds.

A novel approach toward optimized image processing using sigma delta modulation

Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

Implementation of Systolic Multiplier Using Hybrid Multiplexer Dependent Adder

Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems.

PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing.

Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works.

Review on FPGA Implementation of CORDIC Algorithm

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.