Digital Signal Processing Processors Research Articles

Hybrid Radix-16 Booth encoding and Rounding-based Approximate Karatsuba multiplier for Fast Fourier Transform computation in Biomedical signal processing Application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 , delay is 3.01 ns, power consumption is 0.021mW and power delay product is 119 fJ.

Securing Network Information System Design: An Efficient Tool for DSP Undocumented Instruction Mining

As recently studied, the undocumented instructions in embedded processors that may cause catastrophic results for devices have become one of the main threats to system security. To tackle this issue, in this paper, we propose an undocumented instruction mining tool for digital signal processors named DSPUIM that can find out the undocumented instructions from the frequently used Digital Signal Processors (DSP) in network information systems. First, we analyzed the characteristics of the DSP instruction format to compress the instruction search space and improve the instruction search speed. Second, according to the public instruction set of DSPs, we built an instruction disassembly framework that helped us to identify all the undefined instructions. Finally, by testing the executability of undefined instructions automatically, we obtained the undocumented instructions for target DSPs. To demonstrate the effectiveness of our tool, we applied it on ten DSP processors of Texas Instruments (TI) and mined 335 undocumented instructions from them within 5 min. Some undocumented instructions have malicious functions, such as changing registers and denial of service, posing a security threat to the network devices using DSPs.

A Low-Cost, High-Performance Digital Signal Processor (DSP) for Audio Applications

Digital audio signal processing has become increasingly common in multimedia systems as a result of the development of general-purpose digital signal processors (DSP processors) and high-precision oversampling analog-to-digital (A/D) converters. Nevertheless, the solution based on standard DSP chips could be too expensive and power-hungry for portable and home entertainment audio systems. As a result, it is necessary to locate an alternative solution that is both low-cost and low-power. In the context of digital audio applications, this paper will describe how a DSP (Digital Signal Processor) is created, as well as how its architecture functions. The proposed digital signal processor (DSP) has six stages of pipeline with a fixed 24-bit data format, and each stage has 125 instructions. The instructions for the audio signal processing are provided in a very specific manner. Each and every command is handled within the confines of a single cycle.

A Design Method for Low-cost and SOPC-based Flexible Lifting Control System

To efficiently reduce the development and production costs of the intelligent lifting control system, we introduce a design method for the intelligent lifting system with client-server architecture. We replace DSP processor core or DSP (Digital Signal processor) core with Nois II soft-core processor so that the design and production costs can be effectively cut. By replacing DSP processor or DSP processor core with Nois II soft-core processor, the design and production costs can be significantly reduced. In our design, loop vector control units work as a server processor, and a central computing unit with four independent multipliers and two adders is employed, with the implementation method based on a state machine. The experimental results prove effective in reducing resource requirements for FPGA (Field Programmable Gate Array), show that the proposed method can be successfully applied to the implementation of a complete intelligent flexible lifting control system on a low-end Altera Cyclone FPGA, and servo motor control achieves better dynamic performance

Implementation of a Novel, Fast and Efficient Image De-Hazing Algorithm on Embedded Hardware Platforms

Improving the visibility of hazy images is desirable for robot navigation, security surveillance, and other computer vision applications. The presence of fog significantly damages the quality of the captured image, which does not only affect the reliability of the surveillance system but also produce potential danger. Therefore, developing as well as implementing a simple and efficient image de-hazing algorithm is essential. The reconfigurable computing devices like Field Programmable Gate Array and Digital Signal Processing (DSP) processors are used to implement these image processing applications. Several strategies are available for configuring these reconfigurable devices. In this paper, two approaches for hardware implementation of image de-hazing algorithm are presented. The pixel wise and gray image-based de-hazing algorithm is proposed in this paper. The key advantage of this proposed method is to estimate accurate transmission map. It eliminates the computationally complex step of refine transmission map as well as halos & artifacts in the recovered image and achieves faster execution without noticeable degradation of the quality of the de-hazed image. The proposed method is initially verified in MATLAB and compared with the existing four state-of-art methods. This algorithm is implemented on two different hardware platforms, i.e., DSP Processor (TMS320C6748) with floating pointing operations and Zynq-706 fixed-point operations. The performance comparison of hardware architectures is made with respect to Average Contrast of the Output Image, Mean Square Error, Peak Signal to Noise Ratio, Percentage of Haze Improvement and Structural Similarity Index (SSIM). The results obtained show that Zynq-706-based hardware implementation processing speed is 1.33 times faster when compared to DSP processor-based implementation for an image dimensions of $$256\times 256$$ .

Using machine learning techniques for DSP software performance prediction at source code level

Efficient performance prediction at the source code level is essential in reducing the turnaround time of software development. In this paper, we introduce a new prediction model, which combines several machine learning algorithms, such as KNN, clustering, similarity, sample and attribute weighting with multiple linear regression techniques, to predict the execution time of Digital Signal Processing (DSP) software at the source code level. Prediction at source code level tends to both under-predict the performance for certain testing samples and over-predict for some other samples. Therefore, we propose a new algorithm called MAX/MIN algorithm to select the best-predicted execution time. To validate the new model, we measure experimentally the execution time of a set of functions selected from PHY DSP Benchmark and run them on TIC64 DSP processor. It is observed that the average absolute relative prediction error is less than 10% between the computed performance from the new model and the actual measured execution time.

Implementation of Parallel and Pipeline Scheme in the Standard Floating Point Adder to Improve the Speed

In real time Signal Processing applications, the analogue signal is over sampled as per the Nyquist criterion in order to avoid the aliasing effect. Floating Point (FP) adder is used in the floating point Multiplier Accumulator Content (MAC) for real time Digital Signal Processing(DSP) applications. The heart of any real time DSP processor is floating point MAC. Floating Point MAC is constructed by Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters. FIR filters are stable than IIR filters because the impulse response is finite in FIR. Hence, for stable applications FIR filters are preferred. These FIR filters are intern constituted by FP adder, FP multiplier and shifter. In conventional floating point adder the two floating point numbers are added in series. Series means one after the other so the computation speed is less. In series fashion adding the floating point numbers means definitely it furnishes more delay[1] because in the addition of floating point numbers, along with the addition of mantissas; computation is required for both signs and exponents also. Hence, the processing speed is slow for computing the floating point numbers compared with fixed point numbers. Therefore, in order to increase the speed of operation for floating point addition in real time application i.e., to add 16- samples at a time which are in floating notation; a parallel and pipe line technique is going to be incorporated to the two bit floating point architecture. Before developing such novel architecture, a novel algorithm is developed and after, the novel architecture is developed. The total work is simulated by Modelsim 10.3c tool and synthesized by Xilinx 13.6 tool.

Design of Area Efficent 32 Bit Arithmetic and Logic Unit (ALU) for DSP Processors

Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.

Design and Implementation of Motor Control System Based on Industrial Internet

With the development of industrial automation system, industrial Internet by connecting each device even more important. It is based on ARM(Acorn RISC Machine) Cotex-M0 series processor and DSP(Digital Signal Processing) processor researched CAN(Controller Area Network) multi-point real-time data communication system. In ARM Cotex-M0 processor as the master chip, DSP processor as the slave chip. The system uses TCP/IP to transfer data from a client to ARM, ARM using a CAN bus to transmission data to the DSP, and build the modern industrial Internet, realize the motor drive control.

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications.

The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the real-time implementation of neural decoding algorithms on embedded systems has been often overlooked, notwithstanding the impact that limited hardware resources have on the efficiency/effectiveness of any given algorithm. Present study is addressing the optimization of a template matching based algorithm for PNS signals decoding that is a milestone for its real-time, full implementation onto a floating-point digital signal processor (DSP). The proposed optimized real-time algorithm achieves up to 96% of correct classification on real PNS signals acquired through LIFE electrodes on animals, and can correctly sort spikes of a synthetic cortical dataset with sufficiently uncorrelated spike morphologies (93% average correct classification) comparably to the results obtained with top spike sorter (94% on average on the same dataset). The power consumption enables more than 24 h processing at the maximum load, and latency model has been derived to enable a fair performance assessment. The final embodiment demonstrates the real-time performance onto a low-power off-the-shelf DSP, opening to experiments exploiting the efferent signals to control a motor neuroprosthesis.

Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic

Binary addition is one of the primitive operations in computer arithmetic. High performance VLSI integer adders are critical elements in general purpose and digital-signal processing processors since they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. Speed, delay and area are the performance parameters for any adder. Speed can be achieved by means of Square Root Carry Select Adder (SQRT CSLA). Tradeoff between those parameters plays the major role in designing new architecture. From the structure of SQRT CSLA, there is a scope to reduce area by using Zero Finding Logic (ZFC) technique. By using ZFC technique in SQRT CSLA, 16bit architecture has been developed. The modified architecture has reduced area and power when compared to SQRT CSLA Adder. The adder is implemented on Spartan 3E FPGA and is compared with SQRT CSLA. Result analysis Show that the proposed adder gives reduced memory when compared to SQRT CSLA using ZFC.

Optimizations for real-time implementation of H264/AVC video encoder on DSP processor

Real-time H.264/AVC high definition video encoding represents a challenging workload to most existing programmable processors. The new technologies of programmable processors such as Graphic Processor Unit (GPU) and multicore Digital signal Processor (DSP) offer a very promising solution to overcome these constraints. In this paper, an optimized implementation of H264/AVC video encoder on a single core among the six cores of TMS320C6472 DSP for Common Intermediate Format (CIF) (352x288) resolution is presented in order to move afterwards to a multicore implementation for standard and high definitions (SD,HD). Algorithmic optimization is applied to the intra prediction module to reduce the computational time. Furthermore, based on the DSP architectural features, various structural and hardware optimizations are adopted to minimize external memory access. The parallelism between CPU processing and data transfers is fully exploited using an Enhanced Direct Memory Access controller (EDMA). Experimental results show that the whole proposed optimizations, on a single core running at 700 MHz for CIF resolution, improve the encoding speed by up to 42.91%. They allow reaching the real-time encoding 25 f/s without inducing any Peak Signal to Noise Ratio (PSNR) degradation or bit-rate increase and make possible to achieve real time implementation for SD and HD resolutions when exploiting multicore features.

FPGA Implementation of MultiplyAccumulate (MAC) Unit based on BlockEnable Technique

Power dissipation is one of the most important design objectives in integrated circuit, after speed. Digital signal processing (DSP) circuits whose main building block is a Multiply Accumulate (MAC) unit. High speed and low power MAC unit is desirable for any DSP processor. This is because speed and throughput rate are always the concerns of DSP system. This paper explores the design of low power MAC unit with block enable technique to reduce power dissipation. The whole MAC unit is implemented using 90-nm CMOS process technology. The whole MAC unit is operated at 314.268MHz with 1.5V supply voltage. The result analysis shows that the power consumption is reduced by using block enable technique.

Implementation of battery inspection system for building energy management system

In this paper, Battery inspection system (BIS), for a high-speed data transmission in the internal energy management system (EMS) is proposed to reliably maintain charging and discharging batteries. For checking the state of charge (SOC) graph for 12 channels' voltage and temperature, the proposed system was designed to support a controller area network (CAN) interface operation with the speed of 500 kbps, 12-bits successive approximate register (SAR) typed analogue to digital converter (ADC) and a digital signal processing (DSP) processor with the operation speed of 300 MHz. It was conformed that the SOC results were stored in the DSP processor. This BIS system in EMS can be improved with real-time monitoring for the battery information in charging and discharging operation. It is expected to be effective in energy utilisation through BIS.

Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder

Abstr act Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexit ies of algorith ms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array mu ltiplier to achieve high execution speed or to meet the performance demands. A typical imp lementation of such an array mu ltiplier is Braun design. Braun mult iplier is a type of parallel array mult iplier. The architecture of Braun mu ltip lier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. In this research wo rk, a new design of Braun Multiplier is proposed and this proposed design of mult iplier uses a very fast parallel p refix adder (Brent kung Adder) in place of Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the area and delay due to Ripple Carry Adder and performing faster mu ltiplication of two binary numbers. The design is imp lemented using Microwind1, dig ital schemat ics (DSCH)

Design of 32 bit Parallel Prefix Adders

In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer. I. Introduction Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In electronics, an adder or summer is a digital circuits(7) that performs addition of numbers. In many computers and other kind of processors, adders are other parts of the processor, many computers and other kinds of processors, where they are used to calculate addresses, table and similar. The binary adder(7,10) is the one type of element in most digital circuit designs including digital signal processors(DSP) and microprocessor data path units. Therefore fast and accurate operation of digital system depends on the performance of adders (6). Hence improving the performance of adder is the main area of research in VLSI(10) system design. The Conventional adders discussed in section II. The details of R Kogge- Stone adder, Brent-Kung adder and Ladner- Fischer adders are discussed, and the implementation of proposed system is described in section III. The performance and simulation results were presented and discussed in section IV.

Comparison of Cellular Automata and DSP Processors towards DSP Application

In this paper we have emphasized on alternative uses of Cellular Automata (CA) in Digital Signal Processing (DSP). The corollary of the distinction is centered on the parallel nature for both of the processors. For digital signal processing, parallelism has been focused with reference to hardware parallelism as well as software parallelism. Major issues for DSP implementation i.e. sampling, superposition, decomposition, Fourier transformation using CA have been covered in this paper (1). Those discussed results ensure that CA is much efficient to be used for DSP Implementation instead of DSP processors. An ADC transforms an analog signal into digital by choosing sample of the signal at regular intervals and providing the results as a 1D array with suitable sampling frequency, which is determined by Shannon's sampling theorem. By Shannon's sampling theorem, it is essential to sample a signal at a rate greater than double the highest frequency component in the signal in order to keep all the frequency components. In supplementary words, if a signal is sampled at a frequency less than twice the highest frequency of the signal, it may be impossible for a DSP to reproduce the analog waveform from the sampled data precisely.

Correlation Analyzer Project for Teaching Digital Signal Processing with MATLAB and DSP Processor

Digital signal processing (DSP) has become one of key enabling technologies for communications, condition monitoring, multimedia computing, wireless networks and other areas requiring signal and information processing. With the rapid growth of applications of digital signal processing in the world, it has become necessary to introduce these concepts to graduates and undergraduates. Teaching of digital signal processing is carried out not only at the electrical and electronic engineering departments as the most traditional interested in this subject, but also others technical universities are carried out lectures and tutorials. In this paper, a digital signal processing development process is described. It starts from the conceptual algorithm design and computer simulation using MATLAB. After verification of the algorithm, a fixed-point C program is developed for a specific fixed-point DSP processor. This application covers most topics included in a DSP courses performing independent multiple simple experiments. The used methodology enables students and engineers to understand and develop complex fixed-point applications on hardware implementations.

Teaching DSP Implementation: The Big Picture

Starting a digital signal processing (DSP) implementation course can be a daunting task, especially with the advanced DSP algorithms, complex DSP processor architectures and sophisticated development tools that are developed to satisfy consumer demands. These courses can be split into disciplines such as control, audio and video. In this paper the authors are addressing the concerns associated with fast-growing DSP chips and tools and the impact they have on teaching DSP implementation. The authors also provide solutions, advice and suggestions on how to select a DSP, set a DSP implementation course and the associated laboratory hardware and software that fit a specific application.

A practical approach to speech processor for auditory prosthesis using DSP and FPGA

Auditory prosthesis (AP) is a widely used electronic device for patients suffering with severe hearing loss by electrically stimulating the auditory nerve using an electrode array surgically placed inside the inner ear. The AP also known as cochlear implant (CI) mainly contains external Body worn Speech Processor (BWSP) and internal Implantable Receiver Stimulator (IRS). BWSP receives an external sound or speech and generates encoded speech data bits for transmission to IRS via Radio Frequency transcutaneous link for excitation of electrode array placed in the inner ear. Development of BWSP and IRS involves normally the use of either standard microprocessor or microcontroller or digital signal processor (DSP) or FPGA or ASIC devices. Sometimes the performance of the AP system using the standard processors cannot meet the requirement of the intended application. As the selected DSP processor (ADSP2185) from Analog Devices Inc. solely cannot perform the purpose of the speech processor for auditory prostheses, the Xilinx FPGA is added to fulfill the requirement. Combination of a standard processor such as DSP and FPGA may lead to the solution in both prototyping and target operational system. The ADSP2185 processor is used to realize the Continuous Interleaved Sampling (CIS) algorithm for speech signal processing and FPGA is used to realize the speech data encoding algorithm. This paper introduces practical implementations of digital speech processor for use in AP based on DSP ADSP-2185 and Xilinx's FPGA Spartan 3 with the description of practical data. The combination of ADSP2185 and FPGA is used to develop Speech Processor for an auditory prosthesis. FPGA implementation of speech data encoder is initially simulated using ModelSim and interfaced with ADSP2185. The entire embedded application is tested with real time speech signals by using laboratory model IRS and satisfactory results are observed.