Digital Signal Processing Chip Research Articles

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Optimized FIR Filter Using Genetic Algorithms: A Case Study of ECG Signals Filter Optimization

The advancement in technology and the availability of specialized digital signal processing chips have made digital filter design and implementation more feasible in a variety of fields, including biomedical engineering. This paper makes two key contributions. First, it uses a genetic algorithm to optimize the coefficients of finite impulse response (FIR) filters. Second, it conducts a case study on using genetic algorithms to optimize FIR filters for electrocardiogram (ECG) biomedical signal noise removal. The goal of the proposed filter design approach is to achieve the desired signal bandwidth while minimizing the side lobe level and eliminating unwanted signals using a genetic algorithm. The results of a comprehensive analysis show that the genetic algorithm-based filter is more effective than conventional filter designs in terms of noise removal efficiency.

Implementation of Digital Signal Processor for Pulse Doppler Radar

This paper presents the design and implementation of a digital signal processor (DSP) board, utilizing a TMS320C50 family DSP chip, for pulse-Doppler radar systems. Pulse-Doppler radar systems often encounter challenges such as strong clutter, noise, and jamming in dealing with echoes. To overcome these challenges, advanced digital signal processing techniques are employed. The main objective of this paper is to introduce a cost-effective signal processing solution that significantly enhances the performance of the radar system and brings it up to speed with modern radar technologies. The hardware described in this work can also be effectively utilized for implementing various types of signal processing algorithms. Additionally, as a secondary objective, the paper presents the digital realization of a radar detector. Traditionally, this detector was constructed using an analog Doppler filter bank. However, in this work, it is digitally implemented using N digital filters in place of the analog bank. By utilizing the designed DSP board and implementing the radar detector digitally, this paper demonstrates the potential for improved performance and efficiency in pulse-Doppler radar systems. The advancements made in this work contribute to the development of cost-effective and technologically advanced radar systems. The research results are presented for four different wind conditions, showcasing the effectiveness of the proposed approach. Furthermore, the paper suggests an algorithm that combines parametric and non-parametric techniques and provides a detailed explanation of its implementation. Finally, using the non-parametric technique, the probability of detection curves (PD) are simulated with respect to the signal-to-clutter ratio (SCR) for each wind condition, and the simulation results are depicted and compared. The achievements of this paper include the proposal of an efficient approach for clutter suppression in ground surveillance pulse Doppler radar, the comparison of different clutter suppression algorithms, and the development of an algorithm that combines parametric and non-parametric techniques. The simulation results provide valuable insights into the performance of the proposed algorithms under different wind conditions.

Design and Implementation of an Integrated Control Scheme for GaN-Based Multiple Power Converters

In response to the rapid changes in the international energy environment, developing renewable energy (RE)-based distributed generation (DG) and various smart micro-grid systems is crucial for creating a robust electric power grid and new energy industries. In this aspect, there is an urgent need to develop hybrid power systems suitable for coexistent AC and DC power grids, integrated by high-performance wide ban gap (WBG) semiconductor-based power conversion interfaces and advanced operating and control strategies. Due to the intrinsic feature of variation in RE-based power generation, the design and integration of energy storage devices, real-time regulation of power flow, and intelligent energy control schemes are key technologies for further promoting DG systems and micro-grids. This paper investigates an integrated control scheme for multiple GaN-based power converters in a small- to medium-capacity, grid-connected, and RE-based power system. This is the first time that a complete design case demonstrating three GaN-based power converters with different control functions integrated with a single digital signal processor (DSP) chip to achieve a reliable, flexible, cost effective, and multifunctional power interface for renewable power generation systems is presented. The system studied includes a photovoltaic (PV) generation unit, a battery energy storage unit, a grid-connected single-phase inverter, and a power grid. Based on system operation condition and the state of charge (SOC) of the energy storage unit, two typical operating modes and advanced power control functions are developed with a fully digital and coordinated control scheme. Hardware of the GaN-based power converters and digital controllers are designed and implemented. The feasibility and effectiveness of the designed controllers and overall performance of the proposed control scheme are verified with results from simulation and experimental tests on a 1-kVA small-scale hardware system.

Multi-Wavelength Photonic Neuromorphic Computing for Intra and Inter-Channel Distortion Compensations in WDM Optical Communication Systems

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.

End-to-End Interoperable 400-GbE Optical Communications Through 2-km 400GBASE-FR4, 8 × 100-km 400G-OpenROADM and 125-km 400-ZR Fiber Lines

During many years, the WDM domain was dominated by vendors/system suppliers that logically proposed their proprietary solutions and technologies. This proprietary environment offered the space to innovate and allowed an unbelievable progress of optical transport networks that were able to cope with traffic increase for 25 years. Thereby, coherent technology enabled an incredible growth of data rate carried by wavelengths from 10G in the middle of 2000’s decade up to 400G today and soon 800G. However, for data center interconnect (DCI) and metro/regional applications, the lack of openness and interoperability of WDM systems appeared as a real weakness for service providers for both the control (i.e., management) and data (i.e., transceiver) plane. While in the Ethernet area (managed by IEEE) interworking and openness is a reality since a long time, it was not still the case in the WDM domain few years ago. Fortunately, Multi-Source Agreement (MSA) organizations like the Optical Internetworking Forum (OIF), OpenROADM, OpenZR+ and others but also standardization bodies like ITU-T started to break the vendors’ lock-in and fostered the emergence of interoperable WDM transceivers at 100G, 200G, 400G and soon at 800G. In parallel, the great progress of microelectronics and photonic integration also paved the way of a miniaturization of WDM interfaces allowing to have ever more powerful digital signal processing (DSP) engines at higher data rates with drastic power consumption reduction authorizing new fundamental applications like IP over WDM. In this paper, we present for the first time an end-to-end interoperable 400-GbEthernet (GbE) optical transmission on 927-km that integrates the most advanced 400G interoperable pluggable optics covering the needs of Ethernet client (IEEE 802.3 400GBASE), data-center interconnect (OIF 400-ZR), and metro/regional (400G-OpenROADM) networks. The generated 400-GbE data flows seamlessly cross three interoperable sections, i.e., 2-km 400GBASE-FR4, 8 × 100-km 400G-OpenROADM and 125-km 400-ZR standard single-mode fiber lines. The 400G optics used here come from various vendors and embed interoperable DSP chips provided by various suppliers, ensuring the full interoperability of the experimental set-up presented here. The sensitivity to a reconfigurable optical add-drop multiplexer (ROADM) cascade insertion in the OpenROADM section is also investigated.

Conducted Coupling Model and Anti-Interference Filter Design for Digital Control Circuit Under Electrical Fast Transient Noise

Control and protection equipment working in complex electromagnetic environment often suffers from electrical fast transient (EFT) noise, which easily leads to the failure of digital control circuits of the equipment. In order to realize low-cost and effective anti-interference solutions to the failure problem, it is necessary to study the anti-interference quantitative design method of the digital control circuit. In this article, a conducted interference coupling model of the digital control circuit under EFT noise is established. As an important part of the coupling path, the impedance model of the chip is built. A black-box impedance modeling method of voltage regulator chip is proposed based on online measurement. The equivalent impedance model of the digital signal processing (DSP) chip is represented by the high-frequency model of the inductor. The coupling model is validated by comparing the measured results and simulated results of the terminal load port voltage. Then, a measurement and analysis method is presented to obtain the circuit failure threshold. By analyzing EFT test results at different frequencies and amplitudes, the influencing factor of the circuit failure is clarified, and the circuit failure threshold is obtained. Finally, based on the coupling model and the circuit failure threshold, a quantitative design method of an anti-interference filter is developed. The method is validated through filter prototyping for a 5 kHz/+2.0 kV EFT test.

Параметры модуляции современных систем связи

The work consists in describing the types of modulation and their parameters for the selection and construction of modern digital communication networks with multiple subscriber access to network resources and high-speed interconnection. The goal is to systematize communication systems and provide multiple access of network subscribers to resources and high-speed data exchange. Solution method. The article discusses the technologies and standards of modern communication systems in terms of the structure of the construction of receiving and transmitting devices from the conversion of an analog signal into a digital form to the flow of symbolic solutions from the output of the demodulator. The classification of types of wired/wireless communication, communication standards, types of modulation on an analog carrier is carried out. The features of the hardware implementation of receiving and transmitting devices, transmission speeds and operating conditions of communication channels were taken into account. The largest manufacturers of the element base and specialized digital signal processing chips are presented, on which the interfaces of the physical layer of most receiving and transmitting devices of communication systems are implemented. As a result of the analysis, a set of modulation types that are currently used in most communication channels was determined, as well as the main parameters of their operation.

Design of power monitoring system for new energy grid-connected operation based on LoRa and 4G technology

With the large-scale development and utilization of new energy, in order to achieve rapid collection, monitoring and judgment of grid-connected power quality data, this paper proposes a design scheme of a remote acquisition and monitoring system for power data based on LoRa and 4G communication technology. The system uses high-precision A/D to sample various types of electrical energy information such as current and voltage in real time, uses digital signal processor (DSP) chips to complete power quality data calculation, and combines LoRa, 4G and cloud platform technologies to achieve distributed remote metering and centralized monitoring. Experimental results show that the proposed scheme and the designed system have good tracking capability, and meet the requirements of technical specifications to calculate and analyze the conversion efficiency (>90%) and total harmonic distortion (<5%) of the grid-connected system, which improves the safety and monitoring efficiency of new energy power plants connected to the power grid.

Implementation of 12 bit R-2R DAC using cadence(90nm)

An R-2R DAC utilizes less special esteem which is in contrast with to the binary weighed- input DAC. Continuous sampling and measuring of an analog signal occurs over time. This project depends on R-2R Ladder for investing Low power utilization, no dynamic chip and Low DNL. The DAC is executed in a virtuoso device on 90 Nanometer CMOS Technology. The two stages in our projects seems to be Operational Amplifier and R-2R Ladder Digital to analog converters enable transmission of analog signals over digital signal processing chips [1].Two stages are involved in the OP-Amp, the first one being a differential amplifier. We use this Differential Amplifier to obtain high gain and second stage namely Common Source Amplifier. It increases Gain that leaded from the first stage and increases it Output swing. In our project,R-2R DAC is implemented using CADENCE 90nm tool.

High-Performance 10-Transistor Adder Cell for Low-Power Applications

Addition is one of the most fundamental arithmetic operations. Any adder in a digital circuit and system can improve the digital system's performance. Adders, for example, are commonly found in the critical path of many ALUs, processors, and digital signal processing chips. As a result, each of these blocks should execute efficiently and precisely on their own, enhancing the overall performance of the system. Optimizing an adder may lead to overall system optimization. A desirable adder meets all the criteria, such as high speed, low-power dissipation, low leakage power, and small footprint. However, because there is a trade-off between the area, power and, speed.Obtaining the finest adder in terms of speed, power dissipation, leakage power, and area consumed would assist the designer in selecting an adder for the given application. Transmission function adder (TFA), 17-transistor adder (17-TA), 14-transistor adder (14-TA), ripple carry adder (RCA), carry lookahead adder (CLA), and carry-select adder are among the new 2-bit adders suggested and compared (CSL). This research presents a comparative analysis and performance evaluation of adders based on latency, power dissipation, PDP, leakage power, area, and EDP. Simulations are being done using HSPICE software at 28-nm technology with a supply voltage range of 0.7–1.1 V. The suggested adder has a minimum delay and is 8.6% faster than CLA, according to simulation results. When compared to the other adders, it uses the minimum area and has the lowest leakage power. The proposed adder has minimum power delay product.

A Low-Cost, High-Performance Digital Signal Processor (DSP) for Audio Applications

Digital audio signal processing has become increasingly common in multimedia systems as a result of the development of general-purpose digital signal processors (DSP processors) and high-precision oversampling analog-to-digital (A/D) converters. Nevertheless, the solution based on standard DSP chips could be too expensive and power-hungry for portable and home entertainment audio systems. As a result, it is necessary to locate an alternative solution that is both low-cost and low-power. In the context of digital audio applications, this paper will describe how a DSP (Digital Signal Processor) is created, as well as how its architecture functions. The proposed digital signal processor (DSP) has six stages of pipeline with a fixed 24-bit data format, and each stage has 125 instructions. The instructions for the audio signal processing are provided in a very specific manner. Each and every command is handled within the confines of a single cycle.

Implementation of a DSP‐based speed‐sensorless adaptive control for permanent‐magnet synchronous motor drives with uncertain parameters using linear matrix inequality approach

This paper presents a novel speed sensorless adaptive control scheme for the uncertain permanent-magnet synchronous motor (PMSM) drive system using a linear matrix equalities approach with a digital signal processing (DSP) chip. The dynamic model of the PMSM drive with eight error states based on the structure of speed estimator, speed and current controllers is developed. The speed controller, current controller and rotor speed and position estimators are considered simultaneously and designed together. In addition, a three-parameter observer is also designed and the adaptive control law is derived in the light of Lyapunov stability theorem. The objective of this study is to determine the two estimation gains and the six control gains such that the closed-loop system is stable. The stability condition of the system can be characterized in terms of some linear matrix inequalities (LMIs). The LMIs problem can be efficiently solved with the help of MATLAB simulation tool. Differently from the conventional proportional-integral controller, a novel controller with a low-pass filter instead of a pure integrator is proposed. By a suitable adjustment for a design parameter, the steady-state error can also be improved. Numerical solutions of the controller and the estimator gains and simulation examples are provided to illustrate the design procedure and corresponding performances. The experimental results by using a TI TMS320F28335 DSP chip with the speed reference 400, 700, 1000 RPM, respectively and sudden change of the reference demonstrate the performance of the proposed control scheme.

Experimental realization of integrated photonic reservoir computing for nonlinear fiber distortion compensation.

Nonlinearity mitigation in optical fiber networks is typically handled by electronic Digital Signal Processing (DSP) chips. Such DSP chips are costly, power-hungry and can introduce high latencies. Therefore, optical techniques are investigated which are more efficient in both power consumption and processing cost. One such a machine learning technique is optical reservoir computing, in which a photonic chip can be trained on certain tasks, with the potential advantages of higher speed, reduced power consumption and lower latency compared to its electronic counterparts. In this paper, experimental results are presented where nonlinear distortions in a 32 GBPS OOK signal are mitigated to below the 0.2 × 10-3 FEC limit using a photonic reservoir. Furthermore, the results of the reservoir chip are compared to a tapped delay line filter to clearly show that the system performs nonlinear equalisation.

A Novel DSP-Based MPPT Control Design for Photovoltaic Systems Using Neural Network Compensator

In this study, based on the slope of power versus voltage, a novel maximum-power-point tracking algorithm using a neural network compensator was proposed and implemented on a TI TMS320F28335 digital signal processing chip, which can easily process the input signals conversion and the complex floating-point computation on the neural network of the proposed control scheme. Because the output power of the photovoltaic system is a function of the solar irradiation, cell temperature, and characteristics of the photovoltaic array, the analytic solution for obtaining the maximum power is difficult to obtain due to its complexity, nonlinearity, and uncertainties of parameters. The innovation of this work is to obtain the maximum power of the photovoltaic system using a neural network with the idea of transferring the maximum-power-point tracking problem into a proportional-integral current control problem despite the variation in solar irradiation, cell temperature, and the electrical load characteristics. The current controller parameters are determined via a genetic algorithm for finding the controller parameters by the minimization of a complicatedly nonlinear performance index function. The experimental result shows the output power of the photovoltaic system, which consists of the series connection of two 155-W TYN-155S5 modules, is 267.42 W at certain solar irradiation and ambient temperature. From the simulation and experimental results, the validity of the proposed controller was verified.

Design and control algorithm of dual switch forward DC/DC converter with DSP digital control

On the basis of DSP digital signal processing chip TMS320F2812 function as the main control chip of power supply, this paper proposes a dual switch forward topology with RCC converter as auxiliary power supply,the bootstrap drive chip IR2110 as power drive circuit, a dual closed loop control strategy with voltage outer loop and current inner loop, and PID control algorithm using integral separation together with dead zone control. The experimental result show that the power supply structure is easy to operate, and the corresponding control strategy and algorithm effectively improve the stability of the power supply output voltage and the rapidness of the response of the system.

High speed energy efficient multiplier for signal processing

In digital signal processors, computation intensive arithmetic functions such as image smoothing, convolution and filtering frequently involve multiplication-based operations like inner-product generation and accumulation. Multiplication time is the predominate element in determining the execution time of any digital signal processing chip. Switching activity of the functional units in the multiplier contributes to significant amount of power dissipation. This paper presents high speed energy efficient multiplier. By reducing the switching activity and number of computations, the proposed multiplier achieves a better performance in terms of delay and PDP. The proposed high speed energy efficient multiplier is designed using Verilog-HDL and synthesised using Cadence RTL compiler with respect to 180 nm and 90 nm technological libraries. The proposed multiplier shows the delay reduction of 8.95% to 31.40%. The potential benefit of reducing the delay realises a PDP reduction of 13.66% to 26.95%. The performance of the proposed multiplier is verified by implementing it in 16 tap 16-bit coefficient band pass finite impulse response filter. The multiplier used here can be used in signal processing application to obtain energy efficient hardware.

Training deep neural networks for wireless sensor networks using loosely and weakly labeled images

Although deep learning has achieved remarkable successes over the past years, few reports have been published about applying deep neural networks to Wireless Sensor Networks (WSNs) for image targets recognition where data, energy, computation resources are limited. In this work, a Cost-Effective Domain Generalization (CEDG) algorithm has been proposed to train an efficient network with minimum labor requirements. CEDG transfers networks from a publicly available source domain to an application-specific target domain through an automatically allocated synthetic domain. The target domain is isolated from parameters tuning and used for model selection and testing only. The target domain is significantly different from the source domain because it has new target categories and is consisted of low-quality images that are out of focus, low in resolution, low in illumination, low in photographing angle. The trained network has about 7 M (ResNet-20 is about 41 M) multiplications per prediction that is small enough to allow a digital signal processor chip to do real-time recognitions in our WSN. The category-level averaged error on the unseen and unbalanced target domain has been decreased by 41.12%.

DSP Implementation of Neutron Radiation Detection Based on Kalman Filter

Aiming at the situation of nuclear neutron pulse count distortion and low measurement accuracy, a digital processing chip and Kalman filter are designed to replace the traditional hardware filtering method. The system uses TMS320F28335 as the main control chip, and takes advantage of the DSP-specific digital signal processing chip. After using the extended Kalman filter to reduce the noise and filter the pulse neutron count, the experiment proves that the nuclear pulse neutron count measurement after the extended Kalman filter process is stable, and the measurement accuracy has been significantly improved. The overall structure and working principle of the system are introduced, and specific hardware and software design schemes are given.

Cloud Computing and Local Chip-Based Dynamic Economic Dispatch for Microgrids

Dynamic economic dispatch in microgrids is usually realized in a centralized energy management system (EMS). However, centralized systems are subject to single-point failure problems. In rural areas and islands, a failed EMS cannot be recovered in a timely manner due to lack of technical support. In this paper, we propose a cloud and edge computing-based framework to realize dynamic economic dispatch, which is conducted on a local Digital Signal Processor (DSP) chip and a remote cloud computing platform (CCP). Based on the multi-parametric programming algorithm, the dispatch process is divided into two parts: offline calculation and real-time decision making. These calculation tasks can be conducted on the remote cloud computing platform and the DSP chip of the inverter in an arbitrary renewable generator, respectively. The tests are carried out on the Amazon Web Service (AWS) EC2 instance and an autonomous microgrid with DSP TMS320F28335 chip. The results show that the proposed method can obtain the same results as the conventional method, with significantly improved reliability.