High speed energy efficient multiplier for signal processing

Abstract

In digital signal processors, computation intensive arithmetic functions such as image smoothing, convolution and filtering frequently involve multiplication-based operations like inner-product generation and accumulation. Multiplication time is the predominate element in determining the execution time of any digital signal processing chip. Switching activity of the functional units in the multiplier contributes to significant amount of power dissipation. This paper presents high speed energy efficient multiplier. By reducing the switching activity and number of computations, the proposed multiplier achieves a better performance in terms of delay and PDP. The proposed high speed energy efficient multiplier is designed using Verilog-HDL and synthesised using Cadence RTL compiler with respect to 180 nm and 90 nm technological libraries. The proposed multiplier shows the delay reduction of 8.95% to 31.40%. The potential benefit of reducing the delay realises a PDP reduction of 13.66% to 26.95%. The performance of the proposed multiplier is verified by implementing it in 16 tap 16-bit coefficient band pass finite impulse response filter. The multiplier used here can be used in signal processing application to obtain energy efficient hardware.