Digital Signal Processing Applications Research Articles

Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications

Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

Low-power and high-speed approximate multiplier using higher order compressors for measurement systems

At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along with the lower bit compressors are implemented to reduce the delay of the design. This type of digital circuits has much significance in measurement technologies, for enabling fast and accurate measurements. With the use of approximate compressors, the result may be ineffective, but the power consumption and delay are getting reduced. Hence, these proposed multipliers are only implemented the digital signal processing applications, where there is need for combining two or more signals. The proposed multiplier is used for implementing FIR filter resulted 27 ns delay which is far better than the exact multiplier having 119 ns. These multipliers also used in image processing applications and PSNR of image has been employed.

VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier

ABSTRACT Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction.

FPGA Implementation of Data Flow Graphs for Digital Signal Processing Applications

A rapid growth in digital signal processing applications has increased the requirement for high-speed digital systems. Multiprocessor systems are the best choice for these applications. A prior sequence of operations should be applied to the operations that described the nature of these applications before hardware implementation is produced. These operations should be scheduled and hardware allocated. This paper proposes a new scheduling technique for digital signal processing (DSP) applications has been represented by data flow graphs (DFGs). In addition, hardware allocation is implemented in the form of embedded system. A proposed scheduling technique also achieves the optimal scheduling of a DFG at design time. The optimality criteria considered in this algorithm are the maximum throughput within the available hardware resources. The maximum throughput is achieved by arranging the DFG nodes according to their inter-related data dependencies. Then, two nodes can be clustered into one compound task to reduce the overall execution time by minimizing the number of tasks to be executed that minimizing the number of cycles to execute them. Then each task is presented in form of instruction to be executed in the hardware system. A hardware system is composed of one or multiple homogenous pipelined processing elements and it is designed to meet the maximum-rate schedule. Two implementations are proposed of the system architecture according to the number of the processing elements, namely: the serial system and the parallel system. The serial system comprises one processing element where all tasks are processed sequentially, whilst the parallel system has four processing elements to execute tasks concurrently. These systems consist mainly of seven units: central shared memory, state table, multiway function unit buffer, execution array, processing element/s, instruction buffer and the address generation unit. The hardware components were built on an FPGA chip using Verilog HDL. In synthesis results, the parallel system has better system performance by 25.5% than the serial system. While the serial system requires smaller area size, which described by the number of slice registers and the number of the slice lookup tables (LUTs) than the parallel one. The relationship between the number of instructions that are executed in both systems, and the system area and the system performance that presented by system frequency, are studied. By increasing memories size in both systems, the system performance isn’t affected as in a serial system, and it is slightly decreased as the parallel system by 1.5% to 4.5%. In terms of the systems area, both serial system area and parallel system area are increased and in some cases are doubled. The proposed scheduling technique is shown to outperform the retaining technique, which we have chosen to compare with. The serial system has better performance by 19.3% higher system frequency than a retiming technique. And the parallel system also outperforms the retaining technique by 51.2% higher system frequency in synthesis results.

Analysis of New Orthogonal Transforms for Digital Watermarking.

The paper focuses on the application of new orthogonal transforms in digital watermarking. Novel types of transforms and their characteristics are presented. Potential methods for watermark embedding and recovery are also proposed. They assume embedding hidden information in the transform domains using the luminance channel of the original image. Image spectra are obtained by dividing the original image into smaller blocks that then are further processed by performing the forward transform operation. A watermark is embedded by modifying the spectral coefficients with relatively low values. Since there are various types of transforms, the latter process is realized in an adaptive manner. The proposed solutions were evaluated by measuring the level of visual distortion with respect to the total size of the inserted data. Additionally, the bit error rate (BER) in the recovery phase is also analyzed. The elaborated methods seem to be useful for applications in digital signal and image processing where high imperceptibility and low BER are of great importance. New orthogonal transforms were proved to be useful in watermarking tasks, and in some cases, they can even outperform the classic DCT approach.

Linear Version of Parseval’s Theorem

Parseval’s theorem states that the energy of a signal is preserved by the discrete Fourier transform (DFT). Parseval’s formula shows that there is a nonlinear <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">invariant</i> function for the DFT, so the total energy of a signal can be computed from the signal or its DFT using the same nonlinear function. In this paper, we try to answer the question of whether there are linear invariant functions for the DFT, and how they can be found, along with their potential applications in digital signal processing. In order to answer this question, we first prove that the only linear equations that are preserved by the DFT are its orthogonal projections. Then, using Hilbert spaces and adjoint operators, we propose an algorithm that computes all linear invariant functions for the DFT. These linear invariant functions are also shown to be useful and important in a variety of signal-processing applications, particularly for finding some boundaries for transformed signals without explicitly evaluating the DFT, and vice versa. Additionally, using the proposed identities, we demonstrate that the average of a circular auto-correlation function for a large class of signals is preserved by the DFT. Finally, the results reported in this paper are verified for several short-length and long-length DFTs, including a 256-point DFT.

Quantized Corrupted Sensing With Random Dithering

Corrupted sensing concerns the problem of recovering a high-dimensional structured signal from a collection of measurements that are contaminated by unknown structured corruption and unstructured noise. In the case of linear measurements, the recovery performance of different convex programming procedures (e.g., generalized Lasso and its variants) is well established in the literature. However, in practical applications of digital signal processing, the quantization process is inevitable, which often leads to non-linear measurements. This paper is devoted to studying corrupted sensing under quantized measurements. Specifically, we demonstrate that, with the aid of uniform dithering, both constrained and unconstrained Lassos are able to recover signal and corruption from the quantized samples when the measurement matrix is sub-Gaussian. Our theoretical results reveal the role of quantization resolution in the recovery performance of Lassos. Numerical experiments are provided to confirm our theoretical results.

Low energy, long sustainable and high-speed FIR filter based on truncated multiplier with SCG-HSCG adder

In advancement technology and applications like processing sound signals, processing image signals, software define radio signals and so on. In processing of digital systems in all type of devices may be wide range of contraptions and clamors. The result of design the all the athematic devices and performing the addition and multiplication operations need larger space in very large scale implementation. Here, the latest proposed methodology progressed in the design of Finite impulse response filter by redesign the multipliers and adders to introduce new unsigned and signed truncated multiplier and new SCG-HSCG adders. Also different III-Vth semiconductor materials can be used to get high speed filtering operation. In this way to decreases the partials part reduction of design truncated multiplier have more number of adders. The new design handles to replace the SCG-HSCG Adders. This design decreases the logic gates in operations of athematic, additions and multiplications. It also gives the more efficient in the sign and unsigned designs of different digital signal processing applications. This proposed new finite impulse response filter has designed with help of VHDL and Xilinx FPGA-S6LX9. The efficiency of proposed filter with truncated multiplier and SCG-HSCG adder, is compare with the existing all CSLA – Carry Select adder in terms of area, delay, and power. The novel FIR filter design reduces power distribution to the environment while increasing hardware device performance. Furthermore, these kinds of designs take up less space, which means they use less energy and last longer.

A novel multiplication design based on LUT method

Every digital signal processing application performs multiplication operations. The addition and shift operations are part of multiplication operation. Many ideas have been created for computing systems with different design goals in terms of power, area, and speed. Typical architecture of these applications include digital signal processor (DSP), fast Fourier transform (FFT), and Multiply and Accumulate (MAC) unit. This paper offers a new way to increase the speed of DSP systems. This method uses four 2x2 LUT (look-up table) multipliers to demonstrate it at a 4x4 multiplier. The proposed multiplier was created using the Xilinx Vivado software and programmed in the Verilog HDL language. In addition, the delay, area, and power consumption of the proposed multiplier design differ from those of conventional multipliers. The simulation results show that, compared to typical methods, the operation consumes less power, reaching only 3.751 W compared to the conventional multiplier of 4.804 W, and shows lower latency.

Performance Analysis of High Speed and Low Power Binary Adders

In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

Low Area and Power-Efficient FPGA Implementation of Improved AM-CSA-IIR Filter Design for the DSP Application

Digital Signal Processing (DSP) grew enormously in the past few decades and it was extensively practiced for numerous engineering applications like biomedical signal processing, radar signal processing, adaptive antenna design, intelligent control, etc. In DSP, the Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter plays a vital role in the design of a complex signal processing system. Generally, The FIR filters are stable, linear in phase, with fewer finite-precision errors and easy to implement. However, most of the IIR filters are used in signal processing applications due to the less computational complexity which is compared to the FIR filters. Moreover, the IIR filter requires only fewer filter coefficients and requires only less amount storage registers. In this research, an IIR filter is implemented with Array multiplier and Carry Skip Adder (CSA) to improve hardware utilization. The IIR filter input is generated randomly which is stored in Random Access Memory (RAM). Similarly, the coefficient is generated by utilizing the Parks-McClellan algorithm where the generated value is stored in Read Only Memory (ROM). The proposed AM-CSA IIR (Array Multiplier-Carry Skip Adder Infinite Impulse Response) filter performances are evaluated in terms of filter output, Input Output Block (IOB), Look Up Table (LUT), Flip Flops (FF), slices, delay, and fractional delay. Overall the proposed design attained LUT= 115 (0.0564%), FF=40 (0.01%) and IOB= 22 (3.77%) and reduced fractional delay of about 0.0057ns.

RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications

ABSTRACT Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier’s performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.

Implementation of Area Efficient Multiple Passband FIR Filter for 5G Applications

In television, mobile and digital signal processing applications, efficient multiband filters have great usage. The proposed architecture gives the Reconfigurable Finite Impulse Response (FIR) filter with multiple pass bands. Implementation of architecture utilizes FIR filter with control logic and frequency selection circuit. By adjusting the parameters of the filter, proper bandwidth of the pass band can be achieved and the ripple content in the pass band and stop band can be controlled. The efficient way to adjust the bandwidth is to choose the effective value of the filter length and coefficients. The area efficient multiple passband FIR filter using control logic has been proposed with order (n = 4 and 11). Target device that has been selected for implementation is Field Programmable Gate Array (FPGA) Virtex 4 Device. The Look-Up Tables (LUT) utilization for the implemented architecture with length of filter (n = 11) is observed to be 6%.

Low power and area efficient design of fir filter using enhanced clock gating technique

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

Digital ECG Phantom Design to Represent the Human Heart Signal for Early Test on ECG Machine in Hospital

Electrocardiograph (ECG) is a diagnostic tool that can record the electrical activity of the human heart. By analyzing the resulting waveforms of the recorded electrical activity of the heart, it is possible to record and diagnose disease. Given the importance of the ECG recording device, it is necessary to check the function of the ECG recording device, namely by performing a device calibration procedure using the Phantom ECG which aims to simulate the ECG signal. The purpose of this research is to check the ECG device during repairs, besides that the Electrocardiograph (EKG) tool functions for research purposes on ECG signals or for educational purposes. Electrocardiograph (EKG) simulator or often called Phantom ECG is in principle a signal generator in the form of an ECG like signal or a recorded ECG signal. This device can be realized based on microcontroller and analog circuit. The advantage of this simulator research is that the ECG signal displayed is the original ECG recording and has an adequate ECG signal database. ECG This simulator also has the advantage of providing convenience for research on digital signal processing applications for ECG signal processing. In its application this simulator can be used as a tool to study various forms of ECG signals. Based on the measurement results, the error value at BPM 30 and 60 is 0.00% at the sensitivity of 0.5mV, 1.0mV, and 2.0mV, then the measurement results for the error value at BPM 120 are 0.33% and at the BPM 180 value, the error value is 0.22%. From these results, it can be concluded that the highest error value is at BPM 120 with sensitivities of 0.5mV, 1.0mV, and 2.0mV.

Acoustic analysis and digital signal processing for the assessment of voice quality

Purpose:This paper addresses the application of digital signal processing (DSP) techniques to the robust measurement of acoustical features of the human voice. It then addresses the use of regression based techniques for the estimation of grade, roughness, breathiness, asthenia and strain, from these acoustical features. These five properties of voice are the basis of the widely used ‘GRBAS’ characterisation of voice disorders. Method:A well-known cross-correlation technique has been enhanced for more reliably measuring the fundamental frequency of vowels which is crucial for the derivation of acoustic features such as the harmonic-to-noise-ratio, jitter and shimmer. Regression techniques including K-Nearest Neighbour Regression and Multiple Linear Regression are employed for derivation of GRBAS properties. Results:Validation of the enhanced cross-correlation technique against well established published or commercially available techniques has been carried out by analysing synthetic sustained vowels. It was found that the enhanced method is capable of producing more reliable and robust measurements, in the context of our experiments, than the well-established Praat technique and Multi-Dimensional-Voice-Program (MDVP) software, especially in cases where the signal to noise ratio is low. Estimation of GRBAS components using our methods has been found to be in good agreement with traditional GRBAS scoring by speech and language therapists (SLTs). Conclusion:Voice analysis using DSP to extract acoustic features has the potential for objective and computerised GRBAS voice assessment. Such assessment can usefully augment GRBAS assessment as traditionally carried out subjectively by SLTs.

АНАЛИЗ ПРИМЕНИМОСТИ СИСТЕМЫ MATLAB ДЛЯ СИНТЕЗА УПРАВЛЯЕМЫХ ЦИФРОВЫХ РЕКУРСИВНЫХ БИХ-ФИЛЬТРОВ БАТТЕРВОРТА

A number of digital signal processing applications use controlled IIR digital recursive filters.The word " controlled " refers to filters whose structure ratios clearly depend on the cut rate orboundary frequencies. Controlled IIR filters can be synthesized using a variety of tools to computetraditional, uncontrolled IIR filters. The article dealt with the synthesis uncontrolled IIR filters andanalyzed the suitability of the presentation of the results of synthesis for the construction of controlledIIR filters. The design techniques based on MATLAB (2021a) and the fundamental concepts of IIRButterworthdigital filters were described and explained. The composited signal was processed by theanalyzed filter to find whether it met the filtering progress criteria. To check the calculated filters, theSimulink prototype was used, as well as FDA tool of signal processing toolbox. Based on the resultsobtained, a conclusion was made about the applicability of the MAT LAB (2021a) system for thesynthesis of controlled digital recursive IIR-Butterworth filters. The analyzed technique was moreefficient, faster, decreased the tasks and found the results are satisfying.

Application of digital signal processing and machine learning for Electromyography: A review

This paper reviewed the Application of Digital Signal Processing (DPS) and Machine Learning (ML) for Electromyography (EMG) by previous studies. There is a need of the DSP and ML application into the EMG study to classify the signal in order to minimize the EMG noise of signal and the EMG signal characteristic. The common techniques analysis of signal processing is disccussed and compared to identify the best techniques used in order to process from raw data of EMG signal info EMG signal analysis, then some types of machine learning is discussed to identify which types of machine learning have gave the best performance of EMG signal identification and signal characteristic with the highest percentage of the accuracy and efficiency. Digital signal processing and the technique of signal analysis and machine learning for classification method in order to provide the best method and classification for EMG signal.

Design of High Speed and Low Area Confined Multiplier on FPGA

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA

For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.