Digital PWM Research Articles

Asymmetric Dual-Edge Digital Pulsewidth Modulator With an Intrinsic Derivative Action

Controls involving digital pulsewidth modulators (DPWMs) are usually characterized by a non-negligible phase delay due to the analog-to-digital conversion, sampling time, shape of the carrier, and algorithm computation time. Several strategies are proposed in the literature to mitigate this delay. This article features a full DPWM based on the asymmetric dual-edge carrier that successfully overcomes this drawback. Indeed, the proposed structure allows obtaining a derivative action capable of recovering the usual delay associated with the DPWM structures and providing an additional programmable high-frequency phase boost. Besides the operation's description, this article presents an accurate small-signal analysis of the proposed DPWM architecture. The dynamic model is developed using the describing function approach. The proposed architecture and the developed small-signal model are validated in simulations and by experimental tests.

Limit-Cycle Free, Digitally-Controlled Boost Converter Based on DDPWM

In this paper, a digitally controlled boost DC-DC power converter featuring a high-resolution Dyadic Digital Pulse Width Modulator (DDPWM) is proposed to achieve Limit-Cycle oscillations (LCOs)-free operation, high DC accuracy, low output voltage ripple at high switching frequency. The effectiveness of the DDPWM in suppressing the onset of LCOs, increasing DC accuracy, and reducing output ripple is verified by both Simulink/Modelsim co-simulations and experimental testing on a 7-10V input, 13.8V output boost converter operated at 1.17MHz switching frequency. Thanks to the proposed modulator, improvement of more than 6X DC accuracy is achieved compared to a plain digital PWM. Moreover, approximately 3X less output ripple in comparison to a digital PWM with thermometric dithering is achieved.

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit

An optimal control technique for single-phase grid-connected inverter

This paper evaluates the performance of control technique based on Digital Pulse Width Modulation (DPWM) for single-phase grid-connected inverter application. Despite the importance of this synchronization technique, reports on its performance are scarce. The evaluation takes place in two simulation environments: ModelSim and MATLAB/Simulink. The performance of the technique expressed in Total Harmonic Distortion (THD) of Point of Common Coupling (PCC) current of the inverter is found to be 3.62%, a very good result on the standard of IEEE-519. This encouraging performance of this technique will result in injecting more renewable energy into the grid system, resulting in a more sustainable system.

A Dual-Phase Center-Aligned 7-Bit Digital Pulsewidth Modulator for Polar Transmitters

This article presents a dual-phase center-aligned 7-bit digital pulsewidth modulator for the envelope modulation of pulse-modulated polar transmitters (PMPTs). The digital pulsewidth modulator operates at a clock frequency and delivers the modulation frequency of 100 MHz. A delay-locked loop (DLL) consisting of 128 delay cells is used to generate the pulse edges for synthesis of center-aligned pulsewidth modulation (PWM) waveforms. The pulsewidth resolution is 78.1 ps. The measurement results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) of the output pulses are within ±0.4 and ±0.3 LSB, respectively, in the duty cycle range of 2.12%–96.51%. Tested with a 20-MHz 256-quadrature-amplitude modulation (QAM) 5G new radio (NR) signal, the transmitter signal using the output of the modulator achieves the adjacent channel leakage ratio (ACLR) of −33.8 dBc.

Accurate High-Frequency Modeling of the Input Admittance of PWM Grid-Connected VSCs

This article addresses high-frequency admittance modeling of current-controlled voltage source converters (VSCs). Recent studies have shown that harmonic instability may also occur at frequencies above the Nyquist frequency. To form an accurate multiple-frequency model in this frequency range, sidebands that originate from modulation and sampling must be examined. In this article, an accurate small-signal model is developed taking into account an adequate digital pulsewidth modulator (DPWM) representation, which allows to predict dependence of the frequency response on the steady-state dc (SS-dc) operating point. It is shown that when center-pulse sampling is implemented, pulsewidth modulation sidebands do not create additional loops leaving only sampling sidebands to be considered. Using the same approach as for SS-dc operation, a model that accurately represents admittance measurements during sinusoidal ac (S-ac) operation is developed. Its basis is a novel DPWM model suitable for S-ac regime, which allows to predict dependence of the VSC’s input admittance on the grid voltage magnitude. Experimental and simulated admittance measurements, performed on a single-phase two-level VSC during various SS-dc and S-ac regimes, match with the proposed models up to twice the sampling frequency.

Digital V2 Controller IC Using Delta Operator and Improved Average Predictive Control for DC–DC Converters With Fast Transient Response

Owing to its fast transient response, the V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control technique for switching converters has wide potential application prospects. In this article, we present a digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller integrated circuit (IC) for dc–dc switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulsewidth modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-b delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-b hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop (DLL), is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck dc–dc switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

Implementation of HD-SPWM Generation for Voltage Source Inverter Applications

The digital implementation of High-Definition Sinusoidal Pulse Width Modulation (HD-SPWM) achieves a higher accuracy and simplifies hardware design. To generate the digital PWM signal a single BRAM(Block Random Access Memory) is used. The memory allocation of the targeted FPGA device is reduced up to 43%. This reduces the number of slices (logic blocks) and LUTs, used for the implementation of HD-SPWM. The switching and sampling frequency for the generation of HD-SPWM are 20 kHz and 4 MHz respectively. The code is written in Verilog HDL and simulated in Modelsim and synthesized in Xilinx ISE. The Switching frequency achieved is 20 kHz respectively.

Jitter enhanced full digital RF transmitter and PWM RFPA for 5G broadband communications

RFPA (radio frequency power amplifier) based on PWM (pulse width modulation) can be perfect linear without using complicated DPD (digital pre-distortion) hardware. However, PWM RFPA need ultra-high PWM time resolution (less than 10 ps) for wide-band 5G, which is limited by CMOS technologies (can reach 40 ps). It limits the complexity of modulation so that PWM RFPA cannot be really commercialized so far in wideband radio/mobile technologies. This paper presents our contribution by introducing jitter into PWM. For the first time, we demonstrate that jitter can improve the PWM time resolution equivalently reaching less than 2.6 ps. Hence PWM RFPA can be used in 5G supporting 256QAM OFDM modulation based on currently available digital CMOS technologies. We demonstrate that jitter can refine the inherent resolution of PWM hardware circuit modulation. The jitter makes the MCS (modulation and coding scheme) of the bandwidth OFDM system improved from 16QAM to 256QAM in the band n28 of 3GPP 38.101. We also verified that 5G 256QAM OFDM modulation is achievable in the 3GPP band n20, Softbank band28 and NTT Docomo band28. The RMS EVM (root mean square error vector magnitude) of 256QAM OFDM modulation is about −44 dB.

Robust control technique in power converter with linear induction motor

Induction motors are widely used in industrial applications as actuators, thanks to their simplicity of construction, which is subsequently reflected in low-cost maintenance. This paper shows the behavior of a three-phase power converter with a linear induction motor (LIM) as load, using a quasi-sliding control technique for output voltage regulation and a new control technique to control chaos. Digital pulse width modulation (DPWM) techniques are widely used to control electronic power converters. The controller proposed in this paper was designed using zero average dynamic (ZAD) and fixed point inducting control (FPIC) techniques. The ZAD-FPIC control strategy was designed and applied to a three-phase converter with linear induction motor load. Since it is not possible to measure the secondary currents, a secondary current observer was included in the system. Finally, bifurcation diagrams are shown as a technique for tuning controller parameters in ZAD-FPIC controllers. For the illustration of numerical results a simulation of the linear induction motor drive controlled was made by MATLAB/Simulink. The designs were tested in a rapid control prototyping (RCP) system based on digital signal processing (DSP) for dSPACE platform, using the 1103 controller card and control desk interface.

Field programmable gate array-based new fusion control for photovoltaic inverter

This paper proposes a new fusion of digital controls for Photovoltaic (PV) fed DC-DC-AC inverter. The proposed PV-DC-DC-AC design includes the control for voltage regulation of the closed-loop buck converter by combining two duty cycles of Digital Proportional Integral-Digital Pulse Width Modulation (DPI-DPWM) and Maximum Power Point Tracking (MPPT) for one of the DC supply (9V) of the 81-level Trinary Cascaded Hybrid Multi-Level Inverter (TCHMLI). The control for the DC-DC converter is provided by the DPWM techniques, and the TCHMLI requires 16 switching patterns that are to be controlled by the Half Height-Switching Angle Method (HH-SAM). The real-time implementation for the proposed fusion control is verified with a resolution of 28 and 210 bits and validated using Field Programmable Gate Array (FPGA). The hardware result of the proposed photovoltaic inverter is compared with the existing methods and proves to be feasible.

Performance analysis and enhancement of brain emotion-based intelligent controller and its impact on PMBLDC motor drive for electric vehicle applications

ABSTRACT Growing awareness of electric vehicles insists on the necessity of Permanent Magnet Brushless Direct Current Motor (PMBLDCM) worldwide. This paper involves building a simulation model of the complete PMBLDCM drive system using Matlab/Simulink to control the speed and Torque. Using the Simulink model, speed parameters with various controllers of the drive system are studied and analyzed. The conventional PI controller is capable of controlling the speed of the PMBLDC motor. H1owever, it cannot give assurance of the stability of the motor throughout the load variation. In a speed loop, Improved Brain Emotional Learning Based Intelligent Controller (IBELBIC) is proposed in this paper. The proposed IBELBIC-based PMBLDC motor drive system with a rating of 3 phase, 30 V, 400 W, 3000 RPM is implemented using Spartan 3 Field Programmable Gate Array (FPGA) from Xilinx. This paper presents an IBELBIC design for enhancing the speed performance of the drive system at various set speeds and different load conditions of 1.2 Nm load, 0.6 Nm load, and no load. The proposed PMBLDCM drive system is realized with the help of a Very high speed integrated circuit Hardware Description Language (VHDL) programming algorithm of digital Pulse Width Modulation (PWM) generator topology. Various test cases are evaluated under different operating conditions to demonstrate the learning capability and the applicability of the proposed controller. In this paper, simulation validation is done using hardware setup, and experimental results are monitored on a computer using a customized program developed using LabVIEW (Laboratory Virtual Instrumentation Engineering Workbench). Instead of a Data Acquisition (DAQ) card, the Virtual Instrument Software Architecture (VISA) tool of LabVIEW software is used in this work and results in cost minimization of the experimental setup.

Intelligent adjustable-speed drive on an FPGA

This paper addresses the design, simulation and implementation of a PI-like fuzzy controller to adjust the velocity of an armature-controlled DC motor using hardware/software co-design. Fuzzy control and digital pulse width modulation (PWM) techniques are used as computational solution, while the implementation is carried on a reconfigurable hardware platform. This controller is designed with four considerations in mind: design integration, robustness, reduced complexity and flexibility. Computationally intensive tasks are implemented as hardware accelerators using VHDL, data flow and control are implemented in software using system-on-programmable-chip (SoPC) approach. With this paradigm, we get the robustness of fuzzy control, the best of software programmability of Nios®-II and the hardware reconfigurability of the FPGA. The model was synthesised using Quartus®II and targeted at a Cyclone-II FPGA. Computer simulation results show the effectiveness and merit of this process. The real-time applicability of this controller is exemplified on a motor provided with a tachogenerator mounted on its shaft.

Feedback Noise Propagation in Multisampled DC–DC Power Electronic Converters

This article analyzes the propagation of feedback noise in multisampled dc–dc power converters. The analytical calculations for noise attenuation, strictly valid for linear time-invariant systems, are found to offer good predictions for power converters, after suppressing the decimation effects of the digital pulsewidth modulator (DPWM). For control systems that employ a proportional-integral controller, without any digital low-pass filters, the nonlinearity caused by the DPWM decimation is found to saturate the noise attenuation properties, as the multisampling factor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$N$</tex-math></inline-formula> is increased. Strong noise attenuation is enabled using antialiasing digital filters, with a small impact on the dynamic response. For control systems that employ a proportional-integral-derivative controller, increase of the multisampling factor, without any digital filters, causes the amplification of the noise power. Therefore, a greater attenuation of high-frequency components is required to provide a significant noise reduction in the control bandwidth. Even with these antialiasing digital filters, the dynamic response of multisampled control systems is improved compared to double-update. This is proven by the analytical and experimental comparison of various multisampled control strategies in terms of dynamic response and noise attenuation capabilities. The experimental results, from a buck-type converter, match well with simulations and analytical calculations.

Comparison Study of Power Supplies in Real-Time Robust Control Systems of Vertical Plasma Position in Tokamak

The article is devoted to a comparative study of VIs (Voltage Inverters) in the RAO (Relay Auto-Oscillatory) mode and in the multilevel PWM (Pulse Width Modulation) mode as actuators in closed-loop control systems of vertical plasma motion in the T-15MD tokamak. The new digital multilevel PWM controller was developed. Both systems were put under equivalent conditions in terms of the same response to external signals. The discrete robust controller is single for both control systems and has been designed by LMI (Linear Matrix Inequalities) approach using the LPV (Linear Parameter Varying) plant model. The main criteria for comparison are the control power and signal spectrum on the HFC (Horizontal Field Coil). The simulations were performed on the real-time test bed consisting of two real-time target machines connected in a feedback loop “Plant Model – Controller”, to basically bring the system as close to reality as possible. The comparison results have showed the significant superiority of the 9-level PWM VI over the VI in RAO mode according to the selected criteria.

High Frequency Passivity Properties of Grid-Connected Admittance With Double-Sampling Asymmetric Dual-Edge Modulator

Small-signal stability and dynamic interactions among power electronic converters (PECs) and electrical grids are widely analyzed using the impedance-based approach. To reduce such interactions, a desirable feature of PECs is that their admittance exhibits dissipative behavior. Due to control delays, the PEC admittance usually exhibits non-dissipative zones around and above the crossover frequency of the inner control loop, possibly reducing the stability margins of the contemporary electrical grids. This paper proposes the double-sampling asymmetric dual-edge digital pulse-width modulator (ADE-DPWM) as an effective way to improve the passivity properties of the PEC admittance. Even in the digital implementation, the ADE-DPWM features zero delay and almost unity magnitude up to half of the switching frequency. Moreover, this paper examines the influence of ADE-DPWM on the PEC admittance even at higher frequencies, where destabilization of poorly damped grid resonances may be influenced by sampling and pulse-width modulation sidebands. Due to an operating point dependent ADE-DPWM small-signal model, the high-frequency passivity properties highly depend on the steady-state operating point. The analytical predictions are shown to be in excellent agreement with the experimental admittance measurements up to twice the switching frequency for all tested steady-state operating points.

Smooth-Transition Simple Digital PWM Modulator for Four-Switch Buck-Boost Converters

This paper proposes a simple, hardware-efficient digital pulse width modulator for a 4SBB that enables operation in Buck, Boost, and Buck+Boost modes, achieving smooth transitions between the different modes. The proposed modulator is simulated using Simulink and experimentally demonstrated using a 500 W 4SBB converter with 24 V input voltage and 12–36 V output voltage range.

Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

The use of very high-resolution digital pulse width modulators (DPWMs) for high frequency dc-dc converters has been steadily increasing in recent years. However, the resolution of the DPWM formed by counters and comparators is limited when the switching frequency rise above MHz range. Given this limitation, new strategies for DPWM architectures are being designed to increase the resolution of the signals. This article proposes two new DPWMs architectures with the aim of increasing the resolution of trigger signals using field programmable gate arrays (FPGAs). The first proposed architecture is a hybrid DPWM, which integrates a clock manager and a delay line. For this architecture, the delay line is configured using FPGA intellectual properties (IP) blocks. This delay stage allows a fine resolution in the picosecond scale. In addition, an alternative solution has been implemented to generate two signals, the main signal and its complementary one, including high resolution for the dead time, which is also configurable. Both architectures have been tested through static and dynamic tests on two FPGAs of different costs, an Artix-7 (low-cost) and a Kintex-UltraScale 7 (high-cost) by Xilinx.

Hands on Remote Learning Using a DC Motor Controller

An Electrical and Computer Engineering Laboratory exercise has been included in the junior year fall term to partially bridge the theory to practice gap for multiple basic electrical and computer engineering topics. The laboratory investigates facets of power electronics and computer control for students who have recently been introduced to the theory of transistor bridge circuits for voltage polarity control in their electronics class, and digital pulse width modulation for DC motor speed control in their first computer logic class. After brief study of its specification, students follow a lab sequence to set up and instrument a commercial H-bridge to first record polarity and magnitude of output voltages under specified input conditions, and subsequently to observe DC motor response to the same inputs. DC power polarity and averaging through Pulse Width Modulation (PWM), as well as the collateral realities of brushed DC motor noise and logic versus power supply levels become clear to most student for the very first time.

Active-Matrix Micro-LED Display Driven by Metal Oxide TFTs Using Digital PWM Method

This article presents a new micro-light-emitting diode (LED) pixel circuit driven by the digital pulsewidth modulation (PWM) method, in which the threshold voltage compensation of the driving thin-film transistor (TFT) is included. A scan driver integrated by metal oxide (MO) TFTs is also designed to provide the scan signals for pixel circuits array. A micro-LEDs array with <inline-formula> <tex-math notation="LaTeX">$76\,\, \times $ </tex-math></inline-formula> BBB <inline-formula> <tex-math notation="LaTeX">$\times \,\,78$ </tex-math></inline-formula> and a scan driver with 80 stages are simultaneously fabricated by MO TFTs backplane with back-channel etch (BCE) structure. A respective micro-LED display is consequently realized by a peripheral driving system based on a field-programmable gate array (FPGA), which is used as a core control unit to synchronize the scan signals with the data signals. It is shown that the micro-LED in the pixel circuit can operate at a constant current even at the 5-<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> pulsewidth of the emission (EM) signal. The micro-LED display can achieve 256 linear grayscales with an approximately 60 Hz flash rate under the minimum pulsewidth of 40 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> of EM signal.