Abstract
Controls involving digital pulsewidth modulators (DPWMs) are usually characterized by a non-negligible phase delay due to the analog-to-digital conversion, sampling time, shape of the carrier, and algorithm computation time. Several strategies are proposed in the literature to mitigate this delay. This article features a full DPWM based on the asymmetric dual-edge carrier that successfully overcomes this drawback. Indeed, the proposed structure allows obtaining a derivative action capable of recovering the usual delay associated with the DPWM structures and providing an additional programmable high-frequency phase boost. Besides the operation's description, this article presents an accurate small-signal analysis of the proposed DPWM architecture. The dynamic model is developed using the describing function approach. The proposed architecture and the developed small-signal model are validated in simulations and by experimental tests.
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