Digital PWM Research Articles

Digital Pulse Width Modulation Control in Power Electronic Circuits Design

The paper mainly focuses on the digital pulse width modulation (DPWM) control techniques for high performance power electronic circuit design. The problem to be solved in this study addresses the DPWM converter design for DC to DC conversion process. The control techniques have been utilized the Fuzzy Logic Rules Base method for proposed SIMULINK model of high performance power electronic circuit. The analytical calculations for real circuit design have been completed based on the mathematical modeling of the system. The results from the developed SIMULINK model confirm the target specifications of the high performance condition for power electronic circuit which was met the objective of this study. The numerical results have been carried out with the help of MATLAB/SIMULINK.

An Efficient Digital Space Vector PWM Module for 3-φ Voltage Source Inverter (VSI) on FPGA

The realization of digital control circuitry based PWM strategies provides many advantages. It includes better prototyping, higher switching frequency, simple hardware, and flexibility by overcoming the limitations of analog control strategies. In this article, The Digital space vector-based Pulse width Modulation ((DSV-PWM) is designed. The DSV-PWM Module includes, mainly, Xdq reference frame, Sector generation, Square root, switching time generation, Carry-save adder (CSA), and PWM Generation module. These modules are designed using simple logical operations, and combinational circuits to improve the DSV-PWM performance. The DSV-PWM Module is synthesized and implemented on a cost-effective Artix-7 FPGA device. The present work utilizes a < 1% chip area, operates at 597.83 MHz of maximum frequency, and utilizes 110mW of total power on FPGA Device. The DSV-PWM module is also compared with the existing SV-PWM approach with better improvement in hardware constraints like chip area, operating frequency, and dynamic power (mW).

Control technique for single phase inverter photovoltaic system connected to the grid

In photovoltaic system connected to the grid, the main goal is to control the power that the inverter injects into the grid from the energy provided by the photovoltaic generator. The power quality injected into the grid and the performance of the converter system depend on the quality of the inverter current control. In this paper, a control technique for a photovoltaic system connected to the grid based on digital pulse-width modulation (DSPWM) which can synchronize a sinusoidal output current with a grid voltage and control the power factor is proposed. This control is based on the single phase inverter controlled by bipolar PWM Switching and lineal current control. The electrical scheme of the system is presented. The approach is widely explained. Simulations results of output voltage and current validate the impact of this method to determinate the appropriate control of the system. A digital design of the control based on generator PWM using VHDL is proposed and implemented on Field-Programmable Gate Array “FPGA”.The functional structure of this system with digital control has been validated with experimental results.

Design of Dual-Sampling and Adaptive Predictive PID Controller for Buck DC–DC Converters

In this paper, based on the combination scheme of dual-sampling and adaptive predictive PID control, a digital controller for improving the transient performance of Buck DC–DC converters is designed. Due to the inherent loop delay in analog-to-digital (A/D) conversion, the calculation process of the digital controller and digital pulse width modulator (DPWM) of conventional digitally-controlled Buck DC–DC converters limits the system bandwidth and this makes the transient response lower. The designed digital controller can reduce the delay time in analog-to-digital converter (ADC), the digital controller and DPWM of digitally-controlled Buck DC–DC converters. Adaptive predictive control is used to eliminate the delay time of ADC and the digital controller, while dual-sampling scheme is used to reduce the delay time of DPWM in this paper. These are two new control schemes, and they show better performance in improving the transient response than other existing control schemes. Both simulation and experimental results demonstrate that the designed digital controller based on dual-sampling and adaptive predictive PID control is effective in improving the transient performance of Buck DC–DC converters. During experimental verification, for a load step between 0.5[Formula: see text]A and 1.0[Formula: see text]A, the fastest transient recovery time and the overshoot voltage are found to be 102[Formula: see text][Formula: see text]s and 120[Formula: see text]mV, respectively. Compared with the conventional digital PID controller, the transient recovery time and the overshoot voltage of the digital controller designed in this paper are decreased by 40.0% and 27.3%, respectively.

Metode Sederhana untuk Mengendalikan Inverter 5-Tingkat Berbasis Algoritma ¼ λ

The inverter with low voltage harmonics on the output side is a very interesting topic, and widely studied. One of these solutions is a 5-levels inverter: Dual Buck DC-DC Converter - H Bridge Inverter (DBC-HBI). The inverter control methods based on digital sinusoidal pulse width modulation (DSPWM) are commonly implemented by one or a half of the wavelength algorithm (λ). However, one period could be constructed by combining four algorithms by ¼ λ. In this paper, an algorithm of DSPWM based on a ¼ λ algorithm is investigated. The aim of this research is the simplest control and capacities of memory. Finally, a verification of the proposed method was carried out by the experiment in the laboratory. Based on the laboratory tests: 1 λ algorithm has a simple algorithm, but uses large memory, whereas a ¼ λ algorithm more complicated but uses less memory.

THD Reduction in Distributed Renewables Energy Access through Wind Energy Conversion System Integration under Wind Speed Conditions in Tamaulipas, Mexico

In this article, a technique for the reduction of total harmonic distortion (THD) in distributed renewables energy access (DREA) composed of wind turbines is introduced and tested under the wind speed conditions presented in Tamaulipas, Mexico. The analysis and simulation are delimited by a study case based on wind speeds measured and recorded for one year at two highs in the municipality of Soto La Marina, Tamaulipas, Mexico. From this information, the most probable wind speed and the corresponding turbulence intensity is calculated and applied to a wind energy conversion system (WECS). The WECS is composed of an active front-end (AFE) converter topology using four voltage source converters (VSCs) connected in parallel with a different phase shift angle at the digital sinusoidal pulse width modulation (DSPWM) signals of each VSC. The WECS is formed by the connection of five type-4 wind turbines (WTs). The effectiveness and robustness of the DREA integration are reviewed in the light of a complete mathematical model and corroborated by the simulation results in Matlab-Simulink®. The results evidence a reduction of the THD in grid currents up to four times and which enables the delivery of a power capacity of 10 MVA in the Tamaulipas AC distribution grid that complies with grid code of harmonic distortion production.

FPGA Implementation of High Speed Digital Pulse Width Modulator (DPWM) Technique for DC-DC Converter

Objectives: Digital Pulse Width Modulator (DPWM) remains essential element in power controlling devices that command power switch of power converters. The focus of this study is to structure DPWM of FPGA base for DC chopper. Methods: Buck, Boost, Buck and Boost convertor versions are developed in MATLAB-SIMULINK. Verilog coding is performed for Digital Controller to operate for greater rates, which may be incorporated in high speed surroundings; synthesis is completed utilizing Xilinx ISE, along with Behavioral and Period simulation performed with Xilinx Simulator. After affirmation of code it is downloaded on FPGA Spartan 3AN board. The output is confirmed by means of Oscilloscope. Findings/Application: The resulting DPWM is a high speed and less power consuming architecture for Buck, Boost, Buck and Boost DC-DC converter. The utilization of Gray counter and One-hot encoder in DPWM has helped in speed improvement and reduced power consumption. The grey encoding method has fewer states in comparison with the sequential encoding method, which makes them quicker. The output is a Pulse-Width Modulation (PWM) signal, for varying clock frequency and duty cycle. The power consumed by DPWM for various frequencies was verified in comparison with the high frequency DPWM. For 6 MHz frequency, the power consumed by DPWM is 0.01486 w and that by a high frequency DPWM is 0.01486 w. The proposed DPWM can operate at a maximum frequency of 140.298 MHz. This DPWM is best suited for Buck, Boost, and Buck and Boost DC-DC converters. Keywords: DC–DC Converter, Field Programmable Gate Arrays (FPGA), Pulse-Width Modulation (PWM), Spartan, MATLAB, SIMULINK

Design and Implementation of Fpga Based Digital Switching Controller for Dc-Dc Converters Used In System- On- A-Chip Applications

DC-DC converters are electronic devices that are used to change DC electrical power efficiently from one voltage level to another. This paper proposes a new Digital Pulse Width Modulator (DPWM) which generates variable duty cycle PWM pulse and it can be used as switching controller for DC-DC converters used in battery powered portable electronic and mobile devices. DPWM utilizes the advantage of Digital Clock Manager (DCM) present in FPGA to multiply the clock frequency to eliminate the clock skew. The proposed DPWM uses the four bit gray counter and one hot encoder with SR flip flop to generate the PWM pulse whose duty cycle can be varied according to the control signal. To verify the results DPWM was implemented in SPARTAN 3A.

Carrier-Based Digital PWM and Multirate Technique of a Cascaded H-Bridge Converter for Power Electronic Traction Transformers

In the existing technique for power electronic converters with low switching frequency and multiple cells, the sampling frequency is always set at the same value as the control frequency, and the modulating wave in each cell updates itself when its corresponding carrier reaches its peak and valley. In this paper, this implementation scheme is denoted by asymmetrically sampled-pulsewidth modulation (AS-PWM). It is proven that AS-PWM suffers from three defects: further increase of switching frequency is restricted by the available control period and the total cell number; long modulator delay exists and may bring the control system into instability if high crossover frequency is chosen; and spectrum aliasing toward the digital modulating waves may occur and makes the ac input current distorted. Therefore, another implementation scheme of carrier-based digital PWM is recommended in this paper, which is denoted by multisampled PWM (MS-PWM). In MS-PWM, all of the modulating waves update themselves at the same time. The research presented in this paper is based on a power-electronic traction transformer (PETT), which is made up of a cascaded H-bridge converter and several dc/dc converters. For the consideration of scalability, control, and reliability, a star-connected distributed control system is adopted for the PETT equipment. In order to make full use of this distributed hardware, and to improve the control performance with relatively low requirement toward the digital chips, a universal-type multirate structure is proposed in this paper, which is based on the MS-PWM technique. In the proposed structure, the sampling frequency, control frequency, and modulating-wave updating frequency can be separated from the switching frequency, and each of them can be chosen independently according to the practical control demand and the hardware condition. There is no mutual effect between their selections. The influence of the variation of these three frequencies on the control performance is analyzed as well. At last, experimental results based on a five-cell PETT laboratory prototype with a rated power of 30 kW are provided, and all of them verify the effectiveness and correctness of the proposed algorithms.

An All-Digital Low-Noise Switching DC–DC Buck Converter Based on a Multi-sampling Frequency Delta-Sigma Modulation with Enhanced Light-Load Efficiency

This paper presents an all-digital technique to control DC–DC switching buck converters for noise-sensitive low-power applications. The controller is designed based on a multi-sampling frequency digital delta-sigma modulator, whose sampling frequency is adjusted according to the load current. The proposed controller demonstrates the efficiency performance of the digital pulse-width modulation controller counterpart at heavy load while reducing output spikes by 37 dB without any additional processing. At light load, the controller scales down the switching frequency by scaling down delta-sigma modulator sampling frequency. Consequently, light-load efficiency is improved by more than 40% compared to its fixed frequency counterpart. In particular, the proposed solution adopts a unity-gain signal-transfer function delta-sigma modulator that avoids excess phase in the control loop. The proposed technique is compact, scalable and compatible with the standard digital CMOS implementation. Experimental and simulation results characterizing the proposed solution are provided.

A Novel Modular Radiation Hardening Approach Applied to a Synchronous Buck Converter

Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques.

An Isolated Multilevel Quasi-Resonant Multiphase Single-Stage Topology for 380-V VRM Applications

In order to increase the efficiency of modern microprocessor power supplies used in data centers, 380-V dc power distribution systems have been attracting attention due to their high efficiency and high reliability. This paper presents an innovative single-stage approach for 380-V voltage regulator modules (VRMs) based on a quasi-resonant multilevel topology constant on -time operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light-load conditions. This is a unique advantage, which is not possible to establish in the two-stage approach, which is very important in server architectures, and where high efficiency is required even at light-load conditions. This paper analyzes the circuit topology and proposes a control architecture for fast transient response, including current-sharing capabilities. The digital controller has been implemented in 0.16- $\mu$ m lithography together with a digital pulsewidth modulation with a 195-ps resolution and a 40-MS/s 7-bit analog-to-digital converter. Experimental results show an efficiency of 93% for a 120-A 380–1.8-V VRM power supply.

Synchronisation of a distributed control and data acquisition system for modular multi‐level PHIL amplifiers

This research presents a novel technique to synchronise a modular control and data acquisition system for the testing of multi-level power hardware-in-the-loop (PHIL) amplifiers. The methodology is inspired by the precision timing protocol, used to compensate for communications latency between distributed control nodes. It uses a non-conventional digital pulse-width modulation (PWM) technique, phase accumulator carrier pulse-width modulation to achieve carrier synchronisation across the system. A prototype design has been demonstrated on a three-node test bench, showing single clock cycle (10 ns) precision when synchronising a 25 kHz PWM carrier wave, with minimal sensitivity to communications link propagation delays.

A Multiphase Digital Pulsewidth Modulated Polar Transmitter Architecture With Reactive Combiner for Improved Efficiency

This paper presents a new method of reactive-combiner structure to be used as part of a multiphase digital pulsewidth modulated polar transmitter (DPWMPT). It overcomes the limitations of previous implementations of the multiphase pulse-modulated polar transmitter related to terminating pulsewidth modulation (PWM) harmonics located outside the passband, thereby improving both PWM harmonic suppression by using multiphase aliasing-free digital PWM technique and increasing overall efficiency by using reactive combining. For validation, a prototype transmitter was implemented and tested with a 64-QAM 20-MHz bandwidth long-term evolution (LTE) downlink signal with a 7.5-dB peak-to-average power ratio at 2140 MHz. The prototype dual-phase DPWMPT architecture achieved an output power level of 37 dBm and power-added efficiency of 33.5% while passing the stringent spectral requirements of the LTE standard for small-cell base stations using only simply memoryless predistortion correction.

MPPT Charger with PWM Controller for Photovoltaic Based System

Global energy demand is increasing exponentially. This increase in demand causes concern pertaining to the global energy crisis and allied environmental threats. The solution of these issues is seen in renewable energy sources. Solar energy is considered one of the major sources of renewable energy, available in abundance and also free of cost. Solar photo voltaic (PV) cells are used to convert solar energy in to unregulated electrical energy. These solar PV cells exhibition linear characteristics and give very low efficiency. Therefore, it becomes essential to extract maximum power from solar PV cells using maximum power point tracking (MPPT). Perturb and observe (P&amp;O) is one of such MPPT schemes. This paper aims to address the issue of the conventional P&amp;O MPPT scheme under increase solar irradiation condition and its behavior under changed load condition using Digital PWM Controller.

A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA

In this paper, a novel parallel duty cycle control method is proposed to regulate the load voltage of the photo voltaic (PV) fed DC-DC buck converter. The proposed method concentrates on the control of PV fed DC-DC buck converter by fusing the two duty cycles from maximum power point tracking (MPPT) and digital proportional integral-digital pulse width modulation (DPI-DPWM) through the HDPWM algorithm. The fusion of the MPPT algorithms and DPI-DPWM algorithms achieve high precision in the voltage regulation of the PV fed DC-DC buck converter. The proposed parallel duty cycle control is passed through the HDPWM algorithm to compensate the high clocking frequency demand with the design resolution of 210 bits. Further, the design complexity of the HDPWM algorithm is reduced as the resolution of 210 bits is split as 25 and 25 bits for CDPWM and DDPWM respectively. The FPGA based implementation of the proposed parallel duty cycle method includes the synthesizable VHDL code for i) MPPT algorithms, ii) DPI-based DPWM algorithms, iii) Fusing of the MPPT-DPI-DPWM and iv) Passing the fused MPPT-DPI-DPWM through the HDPWM algorithm. The Xilinx Spartan 3A DSP, FPGA implementation is suitable for the proposed parallel duty cycle control method. The hardware results validate the satisfactory PV voltage regulation under continuous changing weather conditions. The transient response of INC-DPI-HDPWM seems to have a faster settling time compared to other MPPT-DPI-DPWM methods. Also, its FPGA implementation proves less area in design and low power consumption compared to the existing methods.

Dead-Time Distortion Shaping

A fully digital algorithm to shape the spectrum of dead-time distortion in power inverters is presented. Dead-time is required to avoid short circuits of the power source by the legs of a power inverter due to the finite turn- on and turn- off times of the switches. Dead-time modifies the pulsewidths of the pulsewidth modulated (PWM) signal causing high harmonic distortion. The proposed approach is based on the time-to-digital conversion of the pulsewidths at the output of the power stage and does not require to measure the sign of the current, which is the preferred approach for dead-time compensation algorithms. The effect of the parasitic capacitance of the switching device that distorts the switching waveform is also analyzed and corrected. Furthermore, the quantization noise produced by digital PWM is also reduced by the proposed approach and has a minimal computational cost. Hardware-in-the-loop simulations are provided to show the effectiveness of the proposed approach, and experimental results using an H-bridge voltage-source inverter are included. A minimum total harmonic distortion plus noise (THD+N) of $\text{0.027}\%$ was achieved for a $\text{1}$ -kHz input driving an inductive load.

Gibbs-Phenomenon-Reduced Digital PWM for Power Amplifiers Using Pulse Modulation

The pulse-modulated polar transmitter (PMPT) uses radio-frequency (RF) phase modulated signal with pulse-width modulated envelope to drive a power amplifier (PA) as a switch to achieve high linearity and high efficiency. However, as the signal bandwidth increases, various non-idealities limit the performance of the PMPT architecture. In this paper, a Gibbs-phenomenon reduction filter is proposed with a partial Fourier series of digital pulse-width modulation (PWM) such that the pulsed signal is more immune to the distortion in nonlinear high-efficiency RF PAs. For validation, a prototype transmitter was tested with a 20-MHz bandwidth 256-QAM 5G new radio (NR) signal at 2.14 GHz. The proposed method achieved a drain efficiency of 28.3%, error vector magnitude (EVM) of 1.67%, and adjacent channel leakage ratio (ACLR) of -45.4 dBc at an output power of 18 dBm using the prototype transmitter. Linearity requirements for base stations were met without the use of any digital predistortion methods.

Open Loop Control of Voltage Across a Three-Phase Resistive Load Fed by Two Level Inverters Controlled by DSP-TMS320F2812

This article presents the design, simulation and implementation of a didactic inverter based on IGBT. The inverter, controlled with the digital pulse width modulation strategy 'DSPWM' by a DSP card from the eZdspTM F2812 platform, feeds a balanced three-phase resistive load. To prove the performance and efficiency of the didactic realized inverter, a fair comparison of its experimental results with those of a compact industrial module 7MBR15SA120 is also presented for different parameters of the control strategy.

A New FPGA-Based Segmented Delay-Line DPWM With Compensation for Critical Path Delays

The duty cycle in digital pulse width modulation (DPWM) whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and interconnects are superimposed on the on-time. The duty-cycle-increment phenomenon affects the regulation performance of converters, especially when the delays are the same magnitude level as switching period. In this paper, a compensation method based on tool command language commands is used to offset the propagation delays. Furthermore, the DPWM applies a counter, phase locked loop, and carry chain to constitute segmented delay-line, while it maintains a wide duty cycle range and a high time resolution. This DPWM is implemented by a low-cost field-programmable gate array Cyclone IV. It achieves a good linearity where R2 is 0.9949 for an 11-bit, 9.375 MHz switching frequency DPWM. The duty cycle range is from 1.52% to 97.81%. Meanwhile, the time resolution and average duty difference are 53 ps and 3.08%, respectively.