Digital Processing Unit Research Articles

Quality evaluation of metal surfaces treatment by wavelet analysis

Purpose. Analyze the effectiveness of using wavelet analysis to assess the quality of metal surfaces. Investigate the possibility of using wavelet analysis in ultrasonic flaw detection. Determine the optimal wavelet families and their criteria for assessing the quality of metal surface processing.
 Research methods. Orthogonal wavelets are considered: Daubechies wavelet, Simlet wavelet and Coiflet wavelet, which provide the possibility of performing a discrete wavelet transform procedure. The criteria influencing the effectiveness of ultrasonic signal filtering by methods using wavelet analysis are considered. Ultrasonic signals were filtered using wavelet functions.
 Results. It has been determined that for successful signal filtering, the selected wavelet method must provide a discrete wavelet transformation and have a similarity in the wavelet function shape in the local features of the ultrasonic signals flaw detector. During the work, a rigid threshold for limiting the detail coefficients of wavelet analysis was chosen, as it is the best for filtering tasks. The filtering efficiency is confirmed by the relatively high signal to noise ratio, as well as by the fact that the shape of the pulse extracted from the defect remained almost unchanged.
 Scientific novelty. When using the Daubechies and Coiflet wavelets as basic functions, as a result of wavelet filtering, it was possible to increase the signal to noise ratio by 20 dB and confidently isolate the useful signal against the background noise, which indicates the prospects of using this kind of transformations in filtering problems.
 Practical value. The obtained solutions can be used for implementation in signal filtering algorithms in digital processing units of automated non-destructive ultrasonic control systems.

Deep Learning Automated System for Thermal Defectometry of Multilayer Materials

Currently, along with growth in industrial production, the requirements for product quality testing are also increasing. In the tasks of defectoscopy and defectometry of multilayer materials, the use of thermal nondestructive testing method is promising. At the same time, interpretation of thermal testing data is complicated by a number of factors, which makes the use of traditional methods of data processing ineffective. Therefore, an urgent task is to search for new methods of thermal testing that will automate the diagnostic process and increase information content of obtained results. The purpose of article is to use the advances in deep learning for processing results of active thermal testing of products made of multilayer materials and development of an automated system for thermal defectoscopy and defectometry of such products. The proposed system consists of a heating source, an infrared camera for recording sequences of thermograms and a digital information processing unit. Three neural network modules are used for automated data processing, each of which performs one of the tasks: defects detection and classification, determination of the defect depth and thickness. The software algorithms and user interface for interacting with system are programmed in the NI LabVIEW development environment.Experimental studies on samples made of multilayer fiberglass have shown a significant advantage of the developed system over using traditional methods for analyzing thermal testing data. The defect classification (determining the type) error on the test dataset was 15.7 %. Developed system ensured determination of defect depth with a relative error of 3.2 %, as well as the defect thickness with a relative error of 3.5 %.

Model-Based Hardware-Software Codesign of ECT Digital Processing Unit

Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.

Research and Implementation of Digital Microscope Image Acquisition System Based on Embedded Linux

<p style="text-align: justify;"><span style="font-family: "times new roman";">With the rapid development of multimedia and Internet in today's society, embedded Linux system also involves many places, and the application of digital microscope is also reused in many industrial manufacturing areas. The main purpose of this paper is to complete the research and implementation of digital microscope image acquisition system based on Embedded Linux, including image acquisition card, logic function, hardware circuit design and image acquisition system. In this paper, the CMOS digital camera is used to connect the CMOS digital camera with the computer through the transmission network, so as to collect the data. In the image preprocessing, the adaptive method based on mean and variance is implemented to correct the gray level of the collected image to avoid high error. In the image registration, the registration algorithm is used to smooth the mosaic place. Then, Sobel algorithm is used to carry out the color transition step by step to eliminate the gap in the image and realize the microscopic image mosaic. The results are as follows: the overall design scheme of the system is designed; the circuit board of digital microscope image acquisition and processing unit based on Embedded Linux is realized; image mosaic is realized by using image preprocessing, registration algorithm and fusion technology, In order to improve the quality of digital microscope image acquisition; through the feasibility test of the system, it is concluded that the performance of the embedded Linux digital microscope image acquisition system proposed in this paper is good, which is worthy of wide application.</span>

A systematic design of novel energy efficient 64-bit parallel-prefix adder

ABSTRACT Advancement in CMOS technology demands to revamp the design of basic functional units in digital systems. The binary addition is the basic operation in digital units like microprocessors, digital signal processors and data processing units in ASICs. Scaling down the technology no longer supports power density and energy-efficient digital architectures. The energy-efficient adder design demands the exploration of recurrence structures, existing algorithms, circuit design techniques, system constraints, energy and delay trade-offs. This paper presents the systematic design approach towards the design of an energy-efficient 64-bit parallel-prefix adder. A novel two-bit sum block reduces the power dissipation and the proposed recurrence algorithm further optimises the overall energy consumption. The 64-bit adder is implemented in static CMOS design and simulated in 45, 32, 22 and 16 nm technology nodes to validate the energy efficiency. In 45 nm technology, the proposed 64-bit parallel-prefix adder consumes 64.61% and 15.3% less energy compared to Brent–Kung and Ling adder respectively whereas in 16 nm technology, the proposed adder consumes 57.54% lesser energy than Brent–Kung adder and 14.28% lesser energy compared to the Ling adder.

ПРИМЕНЕНИЕ ЭФФЕКТА БАРКГАУЗЕНА В МЕХАТРОННЫХ СИСТЕМАХ КОНТРОЛЯ КАЧЕСТВА ЭЛЕКТРОТЕХНИЧЕСКОЙ СТАЛИ

Residual magnetic anisotropy of isotropic electrical steel adversely affects the performance of electrical machines. Mechanical stresses and deformations arising during the manufacture of parts lead to an increase in the anisotropy of the magnetic properties. The aim of this work is to develop a method that makes it possible to assess the degree of residual magnetic anisotropy in finished products. For this, the paper considers the possibility of using the parameters of the Barkhausen effect (EB), reflecting the dynamics of the magnetic structure of the material in alternating magnetic fields. As samples for the study, a set of ready–made stamped plates of the core of a toothed rotor of an electric machine was used. The microstructure of the samples was investigated using a Neopfot–21 metallographic microscope. The studies of the magnetic structure were carried out using the original Barkhausen device for recording magnetic noise, which includes a magnetic noise sensor, a system of amplifying–converting units, and a digital processing unit for measuring information. The results of measurements of the area of the envelope around the circumference of the average diameter and along the teeth of the rotor plate are given, which make it possible to estimate the level of residual anisotropy of isotropic steel by scanning the surface of the tooth rotor plates with a magnetic noise sensor. The data obtained can serve as the basis for the development of a method for controlling the level of magnetic anisotropy of isotropic electrical steels induced in finished products as a result of mechanical processing.

A Noise-Reduced Light-to-Frequency Converter for Sub-0.1% Perfusion Index Blood SpO[Formula: see text] Sensing.

To improve the SpO 2 sensing system performance for hypoperfusion (low perfusion index) applications, this paper proposes a low-noise light-to-frequency converter scheme from two aspects. First, a low-noise photocurrent buffer is proposed by reducing the amplifier noise floor with a transconductance-boost ( gm-boost) circuit structure. Second, a digital processing unit of pulse-frequency-duty-cycle modulation is proposed to minimize the quantization noise in the following timer by limiting the maximum output frequency. The proposed light-to-frequency sensor chip is designed and fabricated with a 0.35- μm CMOS process. The overall chip area is 1 × 0.9 mm 2 and the typical total current consumption is about 1.8 mA from a 3.3-V power supply at room temperature. The measurement results prove the proposed functionality of output pulse duty cycle modulation, while the SNR of a typical 10-kHz output frequency is 59 dB with about 9-dB improvement when compared with the previous design. Among them, 2-3 dB SNR improvement stems from the gm-boosting and the rest comes from the layout design. In-system experimental results show that the minimum measurable PI using the proposed blood SpO 2 sensor could be as low as 0.06% with 2-percentage-point error of SpO 2. The proposed chip is suitable for portable low-power high-performance blood oximeter devices especially for hypoperfusion applications.

Self-interference cancelation in the presence of non-linear power amplifier and receiver IQ imbalance

In the in-band full-duplex(FD) systems, the self-interference (SI) power can be more than 100 dB higher than the power of the received data signal. In order to enable the FD transmission, several SI cancelation stages are needed in a FD transceiver. By combining the cancelation at the radio frequency (RF) with a specially designed antenna and cancelation circuitry and SI cancelation at the digital baseband, the required level of SI cancelation can be achieved even with a non-linear power amplifier. In this paper, a FD transceiver architecture is modeled with simulation tools that allow to use realistic antenna and analog transceiver models and at the same time enable algorithm studies. The analog SI cancelation at the RF is controlled by the baseband digital processing unit, and the tuning of the RF canceler is performed with an automatic gain control enhanced iterative algorithm. The combined cancelation performance of the antenna and RF canceler varies between 62 and 82 dB depending on the studied cases. The digital baseband SI cancelation is based on the Hammerstein model in order to take the power amplifier non-linearity into account. The coefficients of the Hammerstein model are estimated with a self-orthogonalizing adaptive algorithm. When realistic phase noise and IQ imbalance values are taken into account, the SI after all the cancelation stages can decrease the signal-to-interference-and-noise-ratio (SINR) by few decibels (dB). In order to further enhance the SI cancelation, the Hammerstein based SI canceler is extended to cancel also the effect of the receiver IQ imbalance. With the extended baseband canceler, the cancelation performance is mainly limited by the phase noise

Channel-bonding CMOS transceiver for 100 Gbps wireless point-to-point links

5G systems and networks are expected to provide unprecedented data-rate to final users and services, in combination with increased coverage and density. The traffic generated at the edges of the network should be hauled through high capacity data-conveyors. Extremely high data-rate links able to provide optical-fiber like performance in the order of 100 Gbps are required to reduce the cost and increase the flexibility of the network infrastructure deployment. This paper presents a full transceiver architecture based on a channel-bonding radio-frequency front-end operating at millimeter-wave frequencies and digital baseband processing units able to provide such data-rates with a feasible implementation in low-cost CMOS technologies. The baseband section of the receiver includes digital compensation algorithms that allow to cope with some of the radio front-end impairments. The main functionalities of the proposed transceiver architecture are validated in hardware.

Recent Advances in Flexible and Stretchable Sensing Systems: From the Perspective of System Integration.

Biological signals generated during various biological processes are critically important for providing insight into the human physiological status. Recently, there have been many great efforts in developing flexible and stretchable sensing systems to provide biological signal monitoring platforms with intimate integration with biological surfaces. Here, this review summarizes the recent advances in flexible and stretchable sensing systems from the perspective of electronic system integration. A comprehensive general sensing system architecture is described, which consists of sensors, sensor interface circuits, memories, and digital processing units. The subsequent content focuses on the integration requirements and highlights some advanced progress for each component. Next, representative examples of flexible and stretchable sensing systems for electrophysiological, physical, and chemical information monitoring are introduced. This review concludes with an outlook on the remaining challenges and opportunities for future fully flexible or stretchable sensing systems.

Mixed-Precision Deep Learning Based on Computational Memory.

Deep neural networks (DNNs) have revolutionized the field of artificial intelligence and have achieved unprecedented success in cognitive tasks such as image and speech recognition. Training of large DNNs, however, is computationally intensive and this has motivated the search for novel computing architectures targeting this application. A computational memory unit with nanoscale resistive memory devices organized in crossbar arrays could store the synaptic weights in their conductance states and perform the expensive weighted summations in place in a non-von Neumann manner. However, updating the conductance states in a reliable manner during the weight update process is a fundamental challenge that limits the training accuracy of such an implementation. Here, we propose a mixed-precision architecture that combines a computational memory unit performing the weighted summations and imprecise conductance updates with a digital processing unit that accumulates the weight updates in high precision. A combined hardware/software training experiment of a multilayer perceptron based on the proposed architecture using a phase-change memory (PCM) array achieves 97.73% test accuracy on the task of classifying handwritten digits (based on the MNIST dataset), within 0.6% of the software baseline. The architecture is further evaluated using accurate behavioral models of PCM on a wide class of networks, namely convolutional neural networks, long-short-term-memory networks, and generative-adversarial networks. Accuracies comparable to those of floating-point implementations are achieved without being constrained by the non-idealities associated with the PCM devices. A system-level study demonstrates 172 × improvement in energy efficiency of the architecture when used for training a multilayer perceptron compared with a dedicated fully digital 32-bit implementation.

Digital Processing for Accurate Frequency Extraction in IFM Receivers

Extracting the unknown frequency of a radar pulse has been one of the most challenging aspects of instantaneous frequency measurement (IFM) receivers. The conventional IFM receivers are limited in accurate frequency extraction by their design. In this article, a digital processing unit is added to the conventional IFM to extract the frequency with higher accuracy. A 2–4 GHz IFM has been designed combining the compact conventional RF section with the new digital processing unit using a novel efficient frequency extraction algorithm. The algorithm of minimum mean square error (MMSE) estimator is explored for use within the IFM, and it is proven that it can achieve much higher frequency accuracy. The novelty of this article includes both investigation and development of the algorithm to be a good fit for the frequency extraction in IFM receivers and also a digital implementation of the algorithm which meets the minimum requirements of an industrial IFM. The design has been implemented using microstrip filters on Rogers substrate and a Spartan-3E field-programmable gate array (FPGA) processor. The measurement results show promising achievements and verify the principle idea of digital processing for accurate frequency extraction in IFM receivers. The designed and fabricated receiver reaches 1.7 MHz rms frequency error in the frequency band of 2–4 GHz, which is at least $10\times $ improvement with respect to the state-of-the-art works.

Design and Performance Improvement of CNTFET Based Content Addressable Memory (CAM) Cells

The scaling down of transistors is of paramount importance to make ICs and devices more portable and efficient. As it is the most basic component of every electronic device, there is need of finding better and innovative methods of transistor characterization. CNTFET has shown the promise and is best suited for today’s faster digital processing units and Memory devices. Here Carbon Nano Tube (CNT) is characterized for its electrical property and then designed a XOR based CAM cell using CNTFET. Both delay and power analysis for the designed CAM is done.

Plasma Wave Observation in Space Via Scientific Satellites

Space plasmas are essentially collisionless. Kinetic energies of plasmas are transferred through wave-particle interactions. Since plasmas are dispersive media, plasma waves show various features depending on how and which plasma wave modes interact with particles. Plasma wave observations via scientific satellites have a key role in knowing physical processes in space. Plasma wave investigation systems on board satellites are dedicated to the observations of electric field and magnetic field components of plasma waves. They consist of sensors, receivers and an onboard digital processing unit. While dipole antennas are used for electric field sensors, search coil magnetometers or loop antennas are used for magnetic field sensors. Plasma wave receivers are a kind of sophisticated radio receivers. The recent plasma wave receiver is designed as a waveform receiver that can save its mass and size. In addition to waveforms, the waveform receiver provides frequency spectra which are calculated in the digital processing unit from the observed waveforms. The present paper introduces plasma wave observation by scientific satellites on the basis of the latest design of plasma wave investigation systems.

A 763 pW 230 pJ/Conversion Fully Integrated CMOS Temperature-to-Digital Converter With +0.81 °C/−0.75 °C Inaccuracy

A sub-nW fully integrated temperature sensor is presented that digitizes temperature via a capacitive charging time feedback loop controlled by a least significant bit (LSB)-first algorithm. Specifically, an ultra-low-power current reference generator charges two metal–insulator–metal (MIM) capacitors $C_{\mathrm{ top}}$ and $C_{\mathrm{ bot}}$ , generating $V_{\mathrm{ ramp,top}}$ and $V_{\mathrm{ ramp,bot}}$ which are then compared to a constant with temperature (CWT) voltage and a proportional to absolute temperature (PTAT) voltage, respectively. Temperature is then digitized by matching the charging time between the $V_{\mathrm{ ramp,top}}$ and $V_{\mathrm{ ramp,bot}}$ via feedback tuning of $C_{\mathrm{ top}}$ driven by an energy-efficient digital processing unit (DPU) for direct ultra-low-power digital readout. The design is fabricated in 65 nm complementary metal–oxide–semiconductor, and measurement from 12 samples reveals a maximum temperature error of +1.61 °C/−1.53 °C (+0.86 °C/−0.83 °C) and +0.81 °C/−0.75 °C when operating from 0 °C to 100 °C after two-point (three-point) calibration without and with trimming, respectively. Operating from a 0.5 V supply, the 12 samples consumed an average power of 763 pW at 20 °C, which after a 0.3 s conversion time results in 230 pJ/conversion.

Development and preliminary results of Xtrim-PET, a modular cost-effective preclinical scanner

We report on development of Xtrim-PET, a prototype low-cost preclinical PET system using high-density analog silicone photomultiplier (SiPM) arrays and pixelated scintillator LYSO:Ce crystals. Channel reduction method is employed to reduce 144 SiPM signals per detector block to 16 energy and 9 fast signals in the detector head. Using these signals, a Digital Front-End (DFE) board calculates energy, position, and time information of incident gamma photon and transmits data packets to a downstream Digital Coincidence Processing Unit (DCPU) in which the coincidence events are extracted in a fully pipelined digital processing fashion for maximum count throughput. The system consists of 10 detector blocks (detector head and DFE board), a DCPU board, and an acquisition computer. Prompt and delayed coincidence events are stored in list mode in the acquisition computer where first hand corrections are applied and 3D sinogram is generated in offline mode. Two-dimensional sinograms are then generated using single-slice rebinning algorithm and iterative image reconstruction methods are employed to generate the 3D image. The developed scanner works in room temperature without additional cooling system and has 180 mm ring diameter. Tomographic image resolution of 1.6, 1.7, and 1.8 mm FWHM was calculated along radial, tangential, and axial directions, respectively. Preliminary investigations were performed using NEMA image quality phantom in addition to rat cardiac and bone scans for preclinical evaluation of the scanner.

Image-Based Flame Detection and Combustion Analysis for Blast Furnace Raceway

Blast furnace tuyere is an important “window” between the inside and outside of blast furnace. Stable and accurate detection of the combustion condition of tuyere raceway plays a significant role in maintaining longevity, safety, and smooth of blast furnace. The adiabatic combustion temperature as a traditional measurable indicator of the raceway combustion condition considers the raceway temperature as a constant. It cannot explain the productivity and quality fluctuations of iron in practical production while the operation parameters are fixed and unchanged. Thus, this paper presents the image-based flame detection system specific to the blast furnace raceway to research the actual combustion condition in the raceway. The system mainly consists of an optical detector to capture raceway images and a digital image processing unit to extract flame features. In this paper, the nonlinear partial least-squares colorimetry and Monte Carlo method with iterative optimization are developed to obtain the temperature distribution of the raceway. Power spectral analysis is used to extract the flame flicker frequency. Massive raceway images captured from 15 raceways of a 2500-m3 blast furnace were used to analyze raceway flames. The results demonstrate that temperature distribution of the raceway can fluctuate in a wide range and considerable temperature nonuniformity exists among the 15 raceways. This case can explain why productivity and quality of iron are unstable under the same operation parameters. And, the detection system performs well in revealing the nature of the raceway combustion condition.

Leveraging Chaos for Wave-Based Analog Computation: Demonstration with Indoor Wireless Communication Signals

In sight of fundamental thermal limits on further substantial performance improvements of modern digital computational processing units, wave-based analog computation is becoming an enticing alternative. A wave, as it propagates through a carefully tailored medium, performs the desired computational operation. Yet, the necessary designs are so intricate that experimental demonstrations will necessitate further technological advances. Here, we show that, counterintuitively, the carefully tailored medium can be replaced with a random medium, subject to an appropriate shaping of the incident wave front. Using tunable metasurface reflect-arrays, we demonstrate our concept experimentally in a chaotic microwave cavity. We conclude that off-the-shelf wireless communication infrastructure in combination with a simple reflect-array suffices to perform analog computation with Wi-Fi waves reverberating in a room.

Development of a digital processing unit for a rhinomanometric signal

Development of a digital processing unit for a rhinomanometric signal

A Low-Cost Tiny-Size Successive Approximation ADC for Applications Requiring Low-Resolution Conversion with Moderate Sampling Rate

The required silicon die area of successive approximation analog-to-digital converters (SA-ADCs) increases rapidly with ADC resolution. In particular, a main design challenge for SA-ADCs is the number of unit capacitors required for the internal charge distribution capacitive-array digital-to-analog converter (DAC), which increases exponentially with a monotonic increase in the number of the output bits. Therefore, the overall performance of the final design is affected by the huge die area and, in turn, the switching energy of the capacitive-array DAC. In this article, a tiny-size MOSFET-only SA-ADC topology is proposed for those applications which require a low-resolution and moderate to high sampling-rate analog-to-digital converters prior to digital processing units. To this end, the widely used metal–insulator–metal (MIM) capacitors of mixed-signal CMOS technologies are replaced with area-efficient MOS capacitors available in every technology. The effectiveness of this implementation is validated through successful simulation of a 5-bit 20 MS/s MOSFET-only SA-ADC in a low-cost 0.18-µm digital CMOS technology. The ADC consumes a total power of 76.88 µW from a 1.2-V voltage supply, while it occupies a die size of only 190 µm2. This area is roughly 40% lower than 310 µm2, the die area of an equivalent design based on MIM capacitors.