Digital Phase-locked Loop Research Articles

A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <–73 dBc Fractional Spur and <–110 dBc Reference Spur in 65 nm CMOS

This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is capable of suppressing both internal spur, i.e., fractional-N spur, and externally coupled spur from input paths. It can be further extended for multi-stage operation for mitigating multiple spur sources. Both theoretical analysis and simulation results are provided in this paper to explore the design tradeoffs of the proposed technique. A proof-of-concept prototype is implemented in 65 nm CMOS. It measures external spur reduction of 15 to 35 dB and the worst-case fractional spur of 73.66 to 117 dBc with 20–50 dB improvement after enabling the cancellation loop. The measured reference spur ranges from 110.1 to 116.1 dBc across the entire DPLL operation range (3.2–4.8 GHz) thanks to design techniques. The measured in-band phase noise achieves 103 dBc at 100 kHz frequency offset and out-of-band phase noise of 122 dBc at 3 MHz frequency offset with integrated phase noise of 38.1 dBc from 10 kHz to 40 MHz.

New Gen Algorithm for Detecting Sag and Swell Voltages in Single Phase Inverter System

In this manuscript, a novel sag and peak detector by means of a delta square operation for a single-phase is suggested. The established sag detector is from a single phase digital phase-locked loop (DPLL) that is founded on a d-q transformation employing an all-pass filter (APF). The d-q transformation is typically employed in the three-phase coordinate system. The APF produces a virtual phase with a 90 deg phase delay, but the virtual phase can not reproduce an abrupt variation of the grid voltage, at the moment in which the voltage sag transpires. As a consequence, the peak value is severely garbled, and settles down gradually. A modified APF produces the virtual q-axis voltage factor from the difference between the current and the former value of the d-axis voltage component in the stationary reference frame. Nevertheless, the amended APF cannot sense the voltage sag and peak value when the sag transpires around the zero crossing points such as 0 deg and 180 deg since the difference voltage is not adequate to sense the voltage sag. The suggested algorithm is proficient to sense the sag voltage through all regions as well as the zero crossing voltage. Furthermore, the precise voltage drop can be obtained by computing the q-axis component, which is relational to the d-axis component. To authenticate the legitimacy of the suggested scheme, the orthodox and suggested approaches are contrasted by means of the simulations and investigational results.

A 5 GHz Fractional-<inline-formula> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional- $N$ frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to delay-based TDC. The nonlinearity error induced by both TDC and DTC is also analyzed and discussed. Fabricated in a 40 nm CMOS technology, the proposed DPLL achieves an in-band phase noise $-$ 104 dBc/Hz and an integrated phase noise 379 $\text{fs}_{\mathrm{rms}}$ in the fractional- $N$ mode. The DPLL operates at 5 GHz with 2.92-mW power dissipation from a 0.9-V power supply. The core parts only occupy 0.09-mm2 active area. The FoM of the DPLL can be as good as $-$ 243.8 dB.

Bandwidth Compensation Technique for Digital PLL

This brief presents a technique for compensating the bandwidth variation of digital phase-locked loops (PLLs) arising due to process, voltage and temperature (PVT) variation induced changes in loop parameters. For a digital PLL with a bang-bang phase detector, the bandwidth also depends on the phase noise level present at the input of the phase detector. The presented technique also compensates for the bandwidth variations induced by variations in phase noise power. The compensation technique is verified by a MATLAB model and transistor-level transient noise simulations.

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A $\Delta \Sigma $ -less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

This paper describes a spread-spectrum clock generation method by utilizing a Δ∑ digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order Δ∑ modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The Δ∑ DPLL employs a two-point modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 ㎓ spread-spectrum clock generator (SSCG) is implemented in 65 ㎚ CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 ㏈ and 11 ㏈ with 10 ㎑ and 100 ㎑ resolution bandwidths respectively, consuming 6.34 ㎽ from a 1 V supply.

Design of Digital PLL Using Optimized Phase Noise VCO

Design of Digital PLL Using Optimized Phase Noise VCO

Unbiased Finite-Memory Digital Phase-Locked Loop

Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme

This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient-based adaptive single-tone spur cancellation scheme. By using the injection-locked ring oscillator, the TDC quantization step is automatically tracked with the period of the digitally controlled oscillator (DCO) over PVT, and hence is free of calibration. The multi-phase TDC further achieves a fine resolution of 7 to 12 ps, depending on the DPLL's operating frequency. The proposed single-tone spur cancellation scheme achieves more than 40 dB spur suppression. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS technology and synthesizes frequencies from 2.7 to 4.8 GHz with a 1V supply, consuming 21.2 mW. The measured in-band phase noise is −92 dBc/Hz at 40 kHz offset, the far out phase noise is −130 dBc/Hz at 3 MHz offset, with a reference spur of −86.5 dBc.

A fast locked and low phase noise all-digital phase locked loop based on model predictive control

An all-digital phase locked loop (ADPLL) taking new approach for design of the loop filter is presented. A feedback loop in the time domain by modeling the DCO and TDC as an appropriate model in the state-space form is proposed. Then, a model predictive control (MPC) method for designing loop filter in order to generate an optimal control signal is employed. The proposed loop filter can overcome latency issue that inevitably exists in most of digital systems. Furthermore, the proposed MPC loop filter achieves rapid transient response time and enables us to model other noise sources resulted from oscillator pulling and flicker noise which are common problems in many modern transceivers and the effects of which can be dramatically removed without degrading the overall phase noise performance. Simulation results confirm the capability of the proposed design and show it is significantly more robustness against these problems compared to conventional digital PLL.

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), $\Delta \Sigma $ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifies the power–jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0–5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 psrms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is −228.5 dB, which is the best among all reported ring-based FNPLLs.

A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.

A Digital PLL Using Oversampling Delta-Sigma TDC

A digital phase-locked loop (DPLL) using a delta-sigma time-to-digital converter $(\Delta\Sigma\text{TDC})$ is presented. This $\Delta\Sigma\text{TDC}$ adopts the oversampling and feedforward techniques to improve the phase noise of the DPLL. The DPLL is fabricated in a 40-nm CMOS process. The proposed $\Delta\Sigma\text{TDC}$ consumes 0.519 mW at a supply of 1.1 V, and its area is 0.0027 mm2. The measured output frequency is 4 GHz, and the division ratio is 128. The power of the DPLL is 3.51 mW, and its rms jitter is 861 fs.

A DPLL Method Applied to Clock Steering

Several closed-loop control methods have dealt with clock steering problems, but parameters for these methods are not easy to choose. In this paper, we propose a new clock steering method, which uses a second-order type-2 digital phase-locked loop (DPLL) equivalent to a two-state Kalman filter with a delay. We derive the approximate expressions of the steady-state Kalman gains, which are equivalent to the DPLL gains. Then, we derive the transfer functions of the approximate DPLL. A brief and effective approach to choosing a parameter is also proposed. Simulation results show that the performance of the time steering error and the frequency stability is quite desirable, and can meet the requirements of generating a local representation of coordinated universal time or a global navigation satellite system time.

A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).

A New Approach on Design of a Digital Phase-Locked Loop

In this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and $H_\infty$ performance. This DPLL is called the deadbeat $H_\infty$ FIR DPLL (DHFDPLL). The proposed DHFDPLL ensures the $H_\infty$ performance against incorrect information on noise and has intrinsic robustness against quantization effects because of the FIR structure. Demonstrative simulations are provided to show that the DHFDPLL exhibits excellent robustness against effects of incorrect noise and quantization compared with the existing DPLLs.

Synchronous Switching of Non-Line-Start Permanent Magnet Synchronous Machines From Inverter to Grid Drives

Non-line-start permanent magnet synchronous machines (NLSPMSMs) are normally considered not able to operate stably under grid drive. However, this paper proposes an effective control strategy to achieve soft start and synchronous switching of NLSPMSMs from inverter to grid drives so that to extend the application field. The system electromechanical model during switching is deduced and analyzed numerically to verify the stability under grid drive. For the control strategy, model-based sliding-mode observer is adopted during soft start for low-cost position sensorless drive, and two digital phase lock loops are used to obtain the phases of grid and inverter voltages for phase tracking. Experiments are carried out on five NLSPMSMs with different rated powers and velocities, and test results show that all these prototypes can be safely switched to grid drive and robust to load variation. Tested waveforms are coincident with numerical analysis, and the system efficiencies of NLSPMSMs under inverter and grid drives are compared.

An effective approach for parameter determination of the digital phase-locked loop in the z-domain

In digital communication systems, typical methodologies in determining loop parameters of the digital phase-locked loop (DPLL) are based on the mapping transformation from the analog domain to the digital domain. However, such transform based algorithms are relatively complicated and not straightforward, and they also cause the problem that loop parameters are affected by the pre-detection integration time greatly. To solve these issues, an effective direct method of determining loop parameters of the second-order DPLL in the z-domain is proposed in this paper. Through ascertaining specific positions of the closed-loop system function's poles inside the right-hand side of the z-plane's unit circle, unknown parameters are calculated directly and flexibly in this method, which enables the DPLL to acquire good low-pass filtering characteristic and system stability. This novel method not only reduces the complexity of solving the parameters, but also eliminates the effect of the pre-detection integration time on loop parameters. Simulation results are provided to confirm the feasibility of the proposed method and to show that the DPLL obtained by this method achieves the similar tracking performance to the discretized PLL.

Implementation of complex digital PLL for phase detection in software defined radar

Software defined radar (SDR) has been the latest trend in developing enhanced radar signal processing techniques for state-of-the-art radar systems. SDR provides tremendous flexibility in reconfigurable design and rapid prototyping capabilities on FPGA platform. To cater real-time processing for high-speed radar, COordinate Rotation Digital Computer (CORDIC) unit has been utilized as a core processing element in a complex digital phase locked loop (DPLL) for digital demodulation of received signal. Since the real-time systems are required to handle extremely high sampling rates, the pipelined architecture of CORDIC processing element has been chosen for its inherent high system throughput. The architecture is optimized in terms of bit-length for better convergence and loop performance of the first order complex DPLL during demodulation. TheBOXCARfilter has been used as a low pass filter in the output stage of the detector for better information recovery from narrow samples with little energy signal without incurring hardware overhead. Extensive MATLAB simulations have been added to show the effectiveness of the design for the application of radar phase detection.