Digital Low-pass Filter Research Articles

A hybrid capsule attention-based convolutional bi-GRU method for multi-class mental task classification based brain-computer Interface

Electroencephalography analysis is critical for brain computer interface research. The primary goal of brain–computer interface is to establish communication between impaired people and others via brain signals. The classification of multi-level mental activities using the brain–computer interface has recently become more difficult, which affects the accuracy of the classification. However, several deep learning-based techniques have attempted to identify mental tasks using multidimensional data. The hybrid capsule attention-based convolutional bidirectional gated recurrent unit model was introduced in this study as a hybrid deep learning technique for multi-class mental task categorization. Initially, the obtained electroencephalography data is pre-processed with a digital low-pass Butterworth filter and a discrete wavelet transform to remove disturbances. The spectrally adaptive common spatial pattern is used to extract characteristics from pre-processed electroencephalography data. The retrieved features were then loaded into the suggested classification model, which was used to extract the features deeply and classify the mental tasks. To improve classification results, the model’s parameters are fine-tuned using a dung beetle optimization approach. Finally, the proposed classifier is assessed for several types of mental task classification using the provided dataset. The simulation results are compared with the existing state-of-the-art techniques in terms of accuracy, precision, recall, etc. The accuracy obtained using the proposed approach is 97.87%, which is higher than that of the other existing methods.

Design and Implementation of Digital Down Converter for WiFi Network

This paper introduces a field-programmable gate array (FPGA)-based digital down converter (DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency of 28.4375 MHz to match the IEEE 802.11ah Wi-Fi HaLow standard. The proposed DDC uses a polyphase mixer(PM) and a resampling filter. The PM adopts parallel coordinate rotation digital computer (CORDIC) processors and lowpass filter arrays to reduce high-speed data rates with minimum resource utilization. Again, the resampling filter employs a cascaded integrator comb (CIC) filter associated with a parallel prefixed adder (PPA) and a multi-channel systolic finite impulse response (FIR) filter implemented with canonical expression, attaining optimum hardware cost. Converting floating-point to fixed-point data types provides significant resource savings. Finally, the improved design is coded in the Xilinx Vivado synthesis tool and successfully tested on the FPGA Kintex-7 device. In contrast to other recent architectures, the proposed design substantially reduces area requirements and power utilization. The Matlab tool verifies the design to achieve an acceptable spurious-free dynamic range (SFDR) of 115 dB.

A low-cost, wireless, 4-channel EEG measurement system used in virtual reality environments

The combination of Virtual Reality (VR) technology and Electroencephalography (EEG) measurements has shown tremendous potential in the fields of psychology and neuroscience research. However, the majority of EEG measurement devices currently available are expensive, bulky, uncomfortable to wear, and difficult to integrate with VR headsets. These limitations have hindered the development of related research fields. This study describes a low-cost (60.07 USD), small-sized, wireless, high-precision, low-power consumption 4-channel EEG measurement system (NeuroVista) for frontal area EEG measurements, which can be used with a VR headset, enabling EEG measurements in VR environments. The system has an input-referred noise of less than 0.9480 μVrms, a common mode rejection ratio of over 96 dB, a measurement resolution of less than 0.1 μV, a bandwidth of 0.5 ∼ 45 Hz, and works at a sampling rate of 250 Hz. It also supports metal dry electrodes and includes a built-in analog bandpass filter, right-leg drive circuit, and built-in digital lowpass filter and notch filter, which can reduce noise during measurement. Researchers can reconstruct the electrode system to measure regions of interest according to their needs.

Signal Processing from the Radiation Detector of the Radiometric Density Meter Using the Low-Pass Infinite Impulse Response Filter in the Measurement Path in the Coal Enrichment Process Control System

One of the most common coal preparations is enrichment in a jig using a float regulation system. The latest solutions propose to compensate for significant measurement errors of the float by introducing a radiometric density meter operating on the principle of gamma radiation absorption into the bottom product discharge zone of the jig. The signal from the radiometric density meter detector is in the form of a sequence of pulses with a Poisson time distribution, which are counted by a counter, as a form of digital low-pass filter. The requirement to maintain accuracy at an appropriate level forces the measurement time to be extended, which worsens the dynamic properties. Changes in the density of the coal–water medium have an unsteady, cyclical course, resulting from the principle of operation of the jig. The research goal was to develop an algorithm for processing the signal from the radiation detector using an IIR filter in the measurement path in a way that ensures optimization of the dynamic properties of the radiometric density meter operating in the control system of the coal enrichment process in the jig. For this purpose, a low-pass IIR filter was introduced into the measurement path to process the signal from the pulse counter. The identified course of the medium density for one cycle (the first) served as a reference signal. A first-order IIR filter was proposed, with a constant parameter selected on the basis of the reference signal and a parameter depending on the time derivative of the identified density of the medium. The mean squared error MSE was adopted as an indicator for assessing the dynamic properties of the radiometric density meter. The results of simulation tests showed that introducing an IIR filter into the measurement path gives better results in terms of the adopted criterion than using a counter with a constant measurement time. The best results (MSE = 2.05 × 10−4) were obtained using an IIR filter with a parameter that is a linear function of the derivative of the medium density over time, determined for one air pulsation cycle and applied in four subsequent cycles. These results were obtained for an adaptive first-order filter with a variable parameter a from the designated range from 0.833 to 0.999, for a measurement time of 2 ms.

Serial digital QAM-modem based on complex band-pass IIR filters with LF-prototypes of Bessel

The article is devoted to the development and implementation of algorithms for the single-channel sequential quadrature amplitude modulation and demodulation based on digital complex band-pass IIR filters with LF-prototypes of Bessel. The use of complex IIR filters of Bessel allows to obtain orthogonal carrier signals which are close in shape to symmetric signals with practical non-overlapping spectra. The procedure for calculating the 4th-order digital low-pass Bessel filter using the generalized bilinear transformation method, which is used in the theory of digital signal processing to convert a continuous-time system into a discrete-time system, is considered. The variants of implementing the digital complex bandpass filters with a sequential structure using the complex delay method are considered, which allows to obtain the block diagrams of complex bandpass filters without additional calculations and to realize the restructuring of the central frequency without changing the frequency response shape by changing only two coefficients in complex delays. The procedure for obtaining of the expression of the impulse response of digital complex band-pass IIR filters of Bessel is considered. With the help of circuit modeling, the amplitude-frequency response and impulse response of such filter are determined. If the IIR filters are used in the modulator, the pulse characteristics of which are infinite and asymmetric, then it is necessary to use digital complex FIR filters consistent with the truncated pulse characteristic in the demodulator. But as an exception, the Bessel digital IIR filter has a phase-frequency response similar in shape closely to the linear one and, accordingly, a pulse response close to the symmetric one. In this case, the same recursive complex Bessel filters, similar to the filter in the modulator, can be used as matched filters in the demodulator. Therefore, the serial block diagram of the modem contains the same complex band-pass IIR filters with LF-prototypes of Bessel. The choice of the central frequency of the channel digital complex bandpass IIR filter is carried out by setting two coefficients. The results of circuit modeling of the data transmission system with the quadrature amplitude modulation (QAM-16) in the Microcap environment are presented, confirming the operability of the proposed option.

An Improved Active Damping Method for Enhancing Robustness of LCL-Type, Grid-Tied Inverters under Weak Grid Conditions.

The conventional proportional-gain-feedback link can only obtain the smallest effective damping region (EDR) due to the control delay among all the active damping methods regarding the capacitor current feedback. The digitally controlled system tends to be unstable when the system resonant frequency reaches the critical frequency caused by the grid impedance variation. To weaken the adverse effect on the system caused by the control delay, phase-lead feedback links are applied along the feedback path to provide phase compensation. By taking the simplicity and reliability of the feedback links into account, this paper proposes an alternative to an ideal differentiator, which consists of the Tustin discrete form of 's' and a digital low-pass filter. This proposed method has an identical phase frequency characteristic as an ideal differentiator but a better magnitude frequency characteristic, and its EDR can reach [0, fs/3]. The system stability analysis is conducted under different resonant frequencies, and under the condition of a weak grid, the co-design approach of the active damper and digital controller is presented. Finally, the experimental results are shown to verify the proposed method.

Performance Enhancement of Single-Phase Two-Stage AC-DC Converter With Reduced DC-Link Capacitance

Single-phase two-stage AC-DC converters employed in electric vehicle (EV) chargers have the tendency to produce low frequency ripple due to input/ output power mismatch, making it necessary to use bulky DC-link capacitors. High voltage ripple at DC-link due to reduced capacitance, prompts poor input power quality and high low-line frequency ripple at the output of secondary-stage. In state-of-art, input power quality in converters with low DC-link capacitance is enhanced by using a digital low-pass filter (LPF). However, employing LPF to sensed DC-link voltage results in a non-optimum dynamic response and deteriorated stability margins. With the objective to improve input power quality, enhance dynamic performance and reduce secondary-side ripple for low valued DC-link capacitance AC-DC converters, a modified unit-template based model predictive (MUT-MPC) and a DC-link feedforward (DFF) controls are presented in this paper. The current feed-forward for the unit-template is controlled by predictive voltage error through an optimization process of cost function to improve input power quality and dynamic performance for primary AC-DC converter. Furthermore, a DC-link feedforward (DFF) control is implemented for secondary DC-DC stage, which reduces the low-frequency current ripple at the load. Finally, to verify the effectiveness of presented multi-objective control method in comparison with traditional controls, MATLAB simulations and experimental results are provided.

The effect of spatial resolution on deep learning classification of lung cancer histopathology

Objective: The microscopic analysis of biopsied lung nodules represents the gold-standard for definitive diagnosis of lung cancer. Deep learning has achieved pathologist-level classification of non-small cell lung cancer histopathology images at high resolutions (0.5–2 µm/px), and recent studies have revealed tomography–histology relationships at lower spatial resolutions. Thus, we tested whether patterns for histological classification of lung cancer could be detected at spatial resolutions such as those offered by ultra-high-resolution CT. Methods: We investigated the performance of a deep convolutional neural network (inception-v3) to classify lung histopathology images at lower spatial resolutions than that of typical pathology. Models were trained on 2167 histopathology slides from The Cancer Genome Atlas to differentiate between lung cancer tissues (adenocarcinoma (LUAD) and squamous-cell carcinoma (LUSC)), and normal dense tissue. Slides were accessed at 2.5 × magnification (4 µm/px) and reduced resolutions of 8, 16, 32, 64, and 128 µm/px were simulated by applying digital low-pass filters. Results: The classifier achieved area under the curve ≥0.95 for all classes at spatial resolutions of 4–16 µm/px, and area under the curve ≥0.95 for differentiating normal tissue from the two cancer types at 128 µm/px. Conclusions: Features for tissue classification by deep learning exist at spatial resolutions below what is typically viewed by pathologists. Advances in knowledge: We demonstrated that a deep convolutional network could differentiate normal and cancerous lung tissue at spatial resolutions as low as 128 µm/px and LUAD, LUSC, and normal tissue as low as 16 µm/px. Our data, and results of tomography–histology studies, indicate that these patterns should also be detectable within tomographic data at these resolutions.

Discrete-Time Adaptive Neural Tracking Control and Its Experiments for Quadrotor Unmanned Aerial Vehicle Systems

For the control of a quadrotor unmanned aerial vehicle, the strong nonlinearities, coupling, and underactuated problem in both positioning and attitude systems of the quadrotor are major challenging issues to be solved. In this article, a discrete-time adaptive dynamic surface control (DSC) scheme for the quadrotor is proposed to obtain a satisfactory tracking performance. The nonlinearities and couplings are overcome by employing the designed robust adaptive DSC nonlinear control method. The underactuated problem is overcome by solving the designed adaptive neural control equations. Also, different from the continuous-time control scheme, the discrete-time control is more suitable for the computer and network control in practicable cases. Furthermore, the digital first-order low-pass filters are constructed to predict the future virtual control signal in the backstepping method, leading to the avoidance of the model transformation problem in the discrete-time backstepping method.

Software Correction of Speed Measurement Determined by Phone GNSS Modules in Applications for Runners

This paper presents the results of a study on software correction of speed measurements taken by GNSS receivers installed in cell phones and sports watches. Digital low-pass filters were used to compensate for fluctuations in measured speed and distance. Real data obtained from popular running applications for cell phones and smartwatches were used for simulations. Various measurement situations were analyzed, such as running at a constant speed or interval running. Taking a very high accuracy GNSS receiver as the reference equipment, the solution proposed in the article reduces the measurement error of the traveled distance by 70%. In the case of measuring speed in interval running, the error could be reduced by up to 80%. The low-cost implementation allows simple GNSS receivers to approach the quality of distance and speed estimation of very precise and expensive solutions.

Design of Digital Low Pass FIR Filter Using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm

In this study, digital low-pass FIR filter is designed using Hybrid Particle Swarm – Grey Wolf Optimization Algorithm (HPSGWO). The purpose of digital FIR filter design with HPSGWO is to optimized filter coefficients that are closest to the characteristics of the ideal filter. The obtained results are compared with PSO, and GWO which were previously used for FIR filters design in the literature. According to the obtained results, HPSGWO has better filter response and less stop band ripple than other methods.

Artificial intelligence-guided, single-lead EKG may be a game-changer for symptom-to-balloon time reduction in ST-elevated myocardial infarction

Abstract Background Over decades, efforts to shave off life-saving minutes from ST-Elevated Myocardial Infarction (STEMI) care centred on reducing door-to-needle and door-to-balloon times. We firmly believe that symptom-to-balloon time should prove a better focus to this end. Challenges come with this goal as it heavily relies on a patient's perception and initiative to seek care, which we deem intelligent and wearable Artificial Intelligence (AI)-driven Single Lead EKG technologies as an attractive solution in modern-day cardiology. Purpose To provide an accurate, accessible, and cost-effective AI-driven Single Lead STEMI detection algorithm that can be embedded into wearable devices and employed in a self-administered fashion. Methods Database: EKG records from Mexico, Colombia, Argentina, and Brazil from April 2014 to December 2019. Dataset: A total of 11,567 12-lead EKG records of 10[s] length with a sampling frequency of 500 Hz, including the following balanced classes: angiographically confirmed and unconfirmed STEMI, branch blocks, non-specific ST-T abnormalities, normal and abnormal (200+ CPT codes, excluding those mentioned above). Cardiologists manually checked the label of each record to ensure precision. Pre-processing: We discard the first and last 250 samples as they may contain a standardisation pulse. The study applied a digital low pass filter of order 5 with a frequency cut-off of 35 Hz. The mean was subtracted from each Lead. Classification: The determined classes were “STEMI” (Including STEMI in different locations of the myocardium – anterior, inferior, and lateral); and “Not-STEMI” (Combination of randomly sample, branch blocks, non-specific ST-T changes, and abnormal records – 25% of each). Training and Testing: A 1-D Convolutional Neural Network was trained and tested with a dataset proportion of 90/10, respectively. A different model was trained and tested for each Lead, using the central 4,500 samples of the records. The last dense layer outputs a probability for each report of being STEMI or Not-STEMI. Lead V2 showed the best overall results. The model was further tested through the same methodology using the best Lead with a subset of the previous data, excluding the unconfirmed STEMI EKG records (Total 7,230 12-lead EKG records for Confirmed Only STEMI dataset). Performance metrics were reported for each experiment and compared. Results Combined STEMI data: Accuracy: 91.2%; Sensitivity: 89.6%; Specificity: 92.9%. Confirmed STEMI Only dataset: Accuracy: 92.4%; Sensitivity: 93.4%; Specificity: 91.4% (Figure 1). Conclusion By assiduously improving the quality of the model's input, we continue to assess our algorithm's performance and reliability for future clinical validation as a potential remote monitoring and early STEMI detection device. Funding Acknowledgement Type of funding sources: None.

Analysis and Design of Signal Noise Reduction for Flight Control System Based on Micro Mechanical Sensor

Three-dimensional profile measurement system is designed based on the Cortex-M3 series processor. Firstly, a digital low pass filter first is design high performance and low computational cost. Then the output signals from the acceleration sensor, magnetic sensor and gyro are sampled and filtered and a signal modulation circuit is designed to process the signal of gyro, which can improve the efficiency of the sensitive device and effectively suppress the zero drift caused by the device itself. Therefor the stability of the three-dimensional profile measurement system is improved greatly.

Discrete-Time Adaptive Decentralized Control for Interconnected Multi-Machine Power Systems with Input Quantization

This study contrives a discrete-time adaptive decentralized control algorithm with input quantization for interconnected multi-machine power systems with SVC. First, a dynamic surface scheme is applied to the excitation controller design, in which first-order digital low-pass filters are used to predict the next virtual control law, which overcomes the model conversion problem in backstepping. Therefore, the controller design and structure are simplified. Further, an improved hysteresis quantizer is utilized for amplitude quantization of control input signals; along with the discretization of time, this achieves digital decentralized control. Finally, semi-global uniformly ultimately boundedness (SGUUB) of the whole control system is demonstrated based on the Lyapunov stability theory, and the effectiveness of the proposed control algorithm is verified on the ModelingTech real-time simulation experimental platform for power electronics.

A simple and fast algorithm for measuring power system frequency

The article presents a new, discrete-time algorithm for measuring power system frequency. The developed algorithm is based on the linear prediction of samples filtered in a low-pass digital filter with a finite impulse response. Properties of the new algorithm have been compared with properties of known algorithms from the literature, such as the cubic zero-crossing, iterative least squares, DFT-based Prony, revised three-level DFT and selected algorithm based on interpolated DFT. Simulation and experimental studies have been carried out. During the research, among others, the influence of noise, harmonics and interharmonics and time changes of frequency have been analysed. The obtained test results present better properties of the developed algorithm in relations to the compared algorithms. The developed algorithm is characterized by a simple structure, high resistance to noise occurring in the analysed signal and speed of operation in response to changes in the measured frequency.

Chopping for over 50 MHz gain‐bandwidth product current sense amplifiers achieving input noise level of 8.5 nV/√Hz

An accurate, high-speed, fully differential difference amplifier for current sensing utilizing the chopper approach was implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. Unlike state-of-the-art solutions, we use a higher chopping frequency in the MHz range due to the bandwidth requirements of the introduced circuits for the latter application, namely, low-side phase-current measurement in motor control circuits. Except the low-pass filter (LPF) effect of the output stage, no additional LPF was integrated in hardware at the output of the circuits. We show that on the other hand a digital LPF, which can be integrated in the field-programmable gate-array (FPGA) logic or microcontroller used for the motor control, offers a higher flexibility in terms of filter design. Weak input signals of only few mV can be reconstructed with a high accuracy. This is demonstrated for a 500 kHz rectangular signal and a chopping frequency of 20 MHz. Note that an input-signal frequency of several hundreds of kHz with harmonics in the MHz region is very challenging for chopper amplifiers. Still, a significant decrease of the input-referred noise is demonstrated, especially cancelling out the 1/f-noise achieving a remaining noise floor of approximately 8.5 nV/√Hz. Overall, the input-referred noise level can be pushed far below 50 μV (root mean square). Moreover, using a quite relaxed second-order Butterworth filter with a 3 dB corner frequency of 1 MHz, input-referred noise levels of 10 μV (root mean square) can be easily achieved at the costs of reduced bandwidth. The lowest achieved input offset is 50 μV. The gain is adjusted by resistive feedback and is approximately 40 dB. Hence, the amplifier is suitable for current sensing in motor control circuits, and a significant reduction of the shunt resistance typically used for this purpose will be possible.

OPTIMIZATION OF CHARGE / DISCHARGE TIME OF ACTIVE FILTER CAPACITORS DURING VOLTAGE FLUCTUATIONS

A voltage regulator on capacitors has been developed for the control circuit of a parallel active filter based on dq-theory with a block of sliding averaging current in the current control circuit i_d. It contains a delay unit, a digital low-pass filter of the first order FIR or IIR (depending on the variant of the considered scheme) and the unit “sgn”, which stabilizes the output signal. The voltage control circuit on the capacitor can be implemented entirely in digital signal processing and used instead of the analog PID controller, which is much more effective if you need to adapt the circuit to the load mode. Most analog filters suffer from phase distortion when signals at different frequencies are delayed by different amounts. Although it is still present in digital IIR filters. FIR filters are usually designed as a “linear phase”, which means that the filter has no phase distortion. Phase distortions occur due to the fact that signals of different frequencies are delayed differently when crossing the filter. For IIR filters, it is necessary to enter an additional factor that will regulate the group delay, during which the filter will delay the signal of a certain frequency. If you do the same for the FIR filter, you will see a straight horizontal line, which means that all signals are delayed by the same amount, which is good and will provide better signal quality. The unit “sgn” does not affect the process of maintaining the voltage on the capacitors and the speed of transients, its role is to enhance the compensatory capacity of the voltage regulator by filtering the digital signal. The selected filter, by automatically stabilizing the voltage on the capacitor provides a stable charge / discharge process of the capacitor and a high level of compensation of higher harmonics without significant additional generation of active power in the network. When used in the context of real-time analog systems, the digital filter sometimes has a problematic delay (input-output time difference) due to analog-to-digital and digital-to-analog conversion and smoothing. It is shown that by optimizing the charge / discharge time of the capacitor of the power active filter it is possible to achieve the minimum duration of the transient process with the minimum values of harmonic distortions.

OPTIMIZATION OF CHARGE / DISCHARGE TIME OF ACTIVE FILTER CAPACITORS DURING VOLTAGE FLUCTUATIONS

A voltage regulator on capacitors has been developed for the control circuit of a parallel active filter based on dq-theory with a block of sliding averaging current in the current control circuit i_d. It contains a delay unit, a digital low-pass filter of the first order FIR or IIR (depending on the variant of the considered scheme) and the unit “sgn”, which stabilizes the output signal. The voltage control circuit on the capacitor can be implemented entirely in digital signal processing and used instead of the analog PID controller, which is much more effective if you need to adapt the circuit to the load mode. Most analog filters suffer from phase distortion when signals at different frequencies are delayed by different amounts. Although it is still present in digital IIR filters. FIR filters are usually designed as a “linear phase”, which means that the filter has no phase distortion. Phase distortions occur due to the fact that signals of different frequencies are delayed differently when crossing the filter. For IIR filters, it is necessary to enter an additional factor that will regulate the group delay, during which the filter will delay the signal of a certain frequency. If you do the same for the FIR filter, you will see a straight horizontal line, which means that all signals are delayed by the same amount, which is good and will provide better signal quality. The unit “sgn” does not affect the process of maintaining the voltage on the capacitors and the speed of transients, its role is to enhance the compensatory capacity of the voltage regulator by filtering the digital signal. The selected filter, by automatically stabilizing the voltage on the capacitor provides a stable charge / discharge process of the capacitor and a high level of compensation of higher harmonics without significant additional generation of active power in the network. When used in the context of real-time analog systems, the digital filter sometimes has a problematic delay (input-output time difference) due to analog-to-digital and digital-to-analog conversion and smoothing. It is shown that by optimizing the charge / discharge time of the capacitor of the power active filter it is possible to achieve the minimum duration of the transient process with the minimum values of harmonic distortions.

Application of Joint Filter Based on EMD and IIR in SINS

Abstract To solve the problem that the interference of vibration noise in the strapdown inertial navigation system (SINS) affects navigation accuracy, a joint noise reduction method based on Empirical Mode Decomposition (EMD) decomposition and Infifinite Impulse Response (IIR) low-pass digital filter was proposed. On the basis of EMD decomposition, Finally, SINS vehicle test is carried out. The results show that the combined noise reduction method based on joint noise reduction method based on EMD decomposition and IIR low-pass digital filter has an obvious effect on the noise reduction of accelerometer signal. After filtering, the horizontal positioning error of INS is better than 0.29 nautical miles, and the navigation accuracy is improved by 31%. Therefore, the joint noise reduction method based on EMD decomposition and IIR low-pass digital filter proposed in this paper can effectively improve the navigation accuracy of SINS.

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.