Digital Logic Gates Research Articles

Modeling and performance analysis of F-functionalized AGNR reconfigurable logic gates

The paper investigated F-functionalized armchair graphene nanoribbons using the density functional theory. The band structures and densities of states of all AGNR configurations demonstrate the semiconducting nature and can be tuned by taking F-passivation at different edges. Based on binding energy calculations, F@edge_100% AGNR found the most stable configuration compared with other AGNRs. F@edge_100% AGNR device is proposed for nanoscale reconfigurable logic gates. Further comprehensive analysis is done for performance parameters i.e. quantum propagation delay (τp), switching energy (Esw), power dissipation (Pd) of the proposed device. F@edge_100% AGNR confirms the less device area, low propagation delay and lower switching energy. Further in F@edge_100% AGNR device, speed is high and power consumption becomes low as compared to CMOS technology. The proposed device shows the potential for futuristic nanoscale low power and high speed reconfigurable digital logic gates.

Meta-mechanotronics for self-powered computation

There is an unceasing quest to create novel forms of intelligent active matter that exhibits sensing, energy harvesting, actuating, computing, and communication functionalities. Realizing such capabilities can provide new road maps to autonomous and electronic materials with numerous applications in robotics, human–machine interfacing, micro/nano-electromechanical systems, and flexible electronics. Here, we introduce “mechanical metamaterial electronics (meta-mechanotronics)” as a platform for designing intelligent matter that can sense external stimuli, self-power and process the information to create an integrated closed-loop control system. We achieve these advanced functionalities by fusing mechanical metamaterials, digital electronics and triboelectric nano energy harvesting technologies. Meta-mechanotronic systems use only their constituent components and integrated nanogenerator mechanisms to perform self-powered mechanical–electrical-logic and information storage operations. Thus, they establish a direct interaction mechanism between the external environment and electronics, which is a radically different approach from conventional electrically-controlled units. We demonstrate digital unit cells as building blocks for meta-mechanotronics to perform various self-powered computation functionalities. Analytical models, numerical simulations and experimental studies are performed to design a suite of electronic mechanical metamaterials capable of synthesizing discrete mechanical configurations, performing binary/ternary computations, and realizing digital logic gates, i.e., AND, OR, XOR, NAND, NOR, and XNOR. We demonstrate the capability of the framework by creating self-powered mechanically-responsive data storage devices that can store various ASCII codes. Further discussion is provided on how meta-mechanotronics and the associated circuitry can lead to developing future mechanical metamaterial computers, complementing traditional electronics with electronics made of mechanical metamaterials.

Origami-based integration of robots that sense, decide, and respond

Origami-inspired engineering has enabled intelligent materials and structures to process and react to environmental stimuli. However, it is challenging to achieve complete sense-decide-act loops in origami materials for autonomous interaction with environments, mainly due to the lack of information processing units that can interface with sensing and actuation. Here, we introduce an integrated origami-based process to create autonomous robots by embedding sensing, computing, and actuating in compliant, conductive materials. By combining flexible bistable mechanisms and conductive thermal artificial muscles, we realize origami multiplexed switches and configure them to generate digital logic gates, memory bits, and thus integrated autonomous origami robots. We demonstrate with a flytrap-inspired robot that captures ‘living prey’, an untethered crawler that avoids obstacles, and a wheeled vehicle that locomotes with reprogrammable trajectories. Our method provides routes to achieve autonomy for origami robots through tight functional integration in compliant, conductive materials.

Design and simulation of piezoelectric MEMS logic gates

In this article, MEMS-based logic gates such as OR, AND, NOT, NOR, and NAND gates with functionalities similar to the electronic digital devices are designed and simulated. The key feature of these logic devices is that the mechanical cantilever structure of the basic piezo-actuator is adapted to operate like a particular digital logic gate based on the digital inputs. Complete analytical modelling for a single piezo-actuator with a correlation between its out-of-plane tip deflection with applied voltage is obtained. The proposed digital logic devices are further validated through simulation using the MEMS CAD tool CoventorWare.

Classical nexus between chiral inducers and achiral silver nanoparticles and integration of the digital XOR logic gate

Achiral silver nanoparticles are modified with amino acids to make the overall chiral nano-assembly. Electrical measurements are performed, and XOR logic gate is implemented.

A gating lever and molecular logic gate that couple voltage and calcium sensor activation to opening in BK potassium channels.

BK channels uniquely integrate voltage and calcium signaling in diverse cell types through allosteric activation of their K+-conducting pore by structurally distinct V and Ca2+ sensor domains. Here, we define mechanisms and interaction pathways that link V sensors to the pore by analyzing effects on allosteric coupling of point mutations in the context of Slo1 BK channel structure. A gating lever, mediated by S4/S5 segment interaction within the transmembrane domain, rotates to engage and stabilize the open conformation of the S6 inner pore helix upon V sensor activation. In addition, an indirect pathway, mediated by the carboxyl-terminal cytosolic domain (CTD) and C-linker that connects the CTD to S6, stabilizes the closed conformation when V sensors are at rest. Unexpectedly, this mechanism, which bypasses the covalent connections of C-linker to CTD and pore, also transduces Ca2+-dependent coupling in a manner that is completely nonadditive with voltage, analogous to the function of a digital logic (OR) gate.

A New Efficient Nanodesign of Composite Gate Based on Quantum Dot Cellular Automata

The development of nanoscale technologies has come from the downsizing of electronic equipment and the inadequacy of CMOS innovation resulting from hybrid circuit establishment and its failure to respond to nanoscale. Quantum-based technologies, like quantum-dot cellular automata (QCA), are likely to succeed the present technologies due to their incredible benefits, like faster processing, smaller footprints and ultra-low energy usage. In arithmetic and comparison circuits, the fundamental gate is frequently used. Arithmetic logic circuits centered on OR, AND and NOT logic gates have a low design complexity. To obtain complicated logic gates, several architectures have been proposed in the QCA. This work offers a QCA composite gate that achieves all critical digital logic gates, including Inverter, OR, AND, NAND, NOR and exclusive gates like XOR and XNOR. All basic logic is generated in a single unit with this architecture. Only 0.09[Formula: see text][Formula: see text]m2 of area, three three-input majority gates, one XOR, three Inverters, and 0.5 clock zones were required for the suggested circuit. As a result, a decrease of 33% in cell count is achieved compared to the previous systems. The design is evaluated and the dissipated energy is analyzed. For the research on power dissipation, the QCADesigner-E simulator is used to verify the final result. The simulation outcomes show that the suggested layout is advantageous over earlier constructions regarding the area, number of cells, clock phases and cost.

EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;5\times $ </tex-math></inline-formula> reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.

Detection of tomato leaf curl New Delhi virus DNA using U-bent optical fiber-based LSPR probes

The detection of Tomato leaf curl New Delhi virus (ToLCNDV) DNA has been presented using U-bent fiber optic sensor (FOS) by an evanescent wave absorption method in the visible region. The localized surface plasmon resonance (LSPR) based FOS was developed by immobilizing gold nanoparticles on the amine-functionalized surface and the receptor probe was prepared by attaching a short segment of the complementary DNA (cDNA) on this surface. Further, the cDNA attachment was confirmed by monitoring the real-time change in LSPR absorption spectra. The conjugation protocol of single-strand DNA (ssDNA) from the viral genome of ToLCNDV was established like antibody-antigen-based assays by observing the real-time change in absorption kinetics. Consequently, a linear correlation between ssDNA concentration and the conjugation-dependent change in refractive index (RI) has been observed. The limit of detection (LOD) using two different cDNA immobilized FOS probes was determined to be 50±10 ng/μL and the change in RI was found 12.5±1.3×10−4 RIU/Abs. From this systematic binding study, a straightforward target-specific sensor has been constructed using a digital electronic logic gate analogy. This device has significant commercial potential for the development of a portable LSPR sensor for real-time detection of plant pathogens in addition to the possibility of multi-target environments.

Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates.

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

Direct‐Writing of 2D Diodes by Focused Ion Beams

AbstractElectronic devices based on 2D materials have exhibited outstanding figures of merit. However, the fabrication of 2D diodes still relies on manual or semi‐automated handling processing. To unleash their commercial potential, the integration of 2D materials into a fully‐automated fabrication line is a critical step. Here, the focused ion‐beam writing as an automated approach to construct lateral diodes on a 2D heterostructure (MoSe2/G) consisting of graphene and MoSe2 is elucidated. Se‐defects generated by focused ion writing endow the 2D heterostructure with unique electronic properties, which allows for the construction of the barrier at the boundary of the writing and non‐writing region. Benefiting from this feature, the ion‐beam‐written heterostructure is used to realize rectifying and current regulating diodes. Exhibiting comparable performance to traditional diodes, the rectifying diode has a rectification ratio of ≈104, while the current regulative diode has a dynamic resistance larger than 4.5 MΩ. Furthermore, to illustrate practical applications of these diodes in digital logic electronics, AND and OR logic gates are directly inscribed on the heterostructure by ion beams. This work demonstrates focused ion‐beam writing as an additional strategy for direct‐writing of 2D diodes on graphene‐based heterostructures.

Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

Position signal detector for linear variable differential transformer

This paper presents the position signal detector for linear variable differential transformer (LVDT) based on RMS-to-DC converter. The proposed detector consists of the differential amplifier, the comparator, the phase detector, the controllable unity-gain inverting/non-inverting amplifier and the RMS-to-DC converter. The proposed technique provides a simple scheme and uses the low cost commercial available devices such as opamp, transistor and digital logic gate. The experimental testing with the commercial LVDT model OP12.5G from Solartron Metrology showing the proposed position signal detector can produce the output voltage corresponding to the measured displacement with satisfactory values and good linearity.

Graphene cantilever-based digital logic gates

Universal logic gates NAND and NOR along with NOT and XOR are successfully implemented using graphene cantilever structures. Three-dimensional (3D) modeling of different graphene cantilever structures is carried out using the COMSOL Multiphysics software. The high electrical conductivity of graphene makes it a better choice for the cantilever beams in this study. A very low actuation voltage of 1.57 V is obtained for a 2-µm-long, 0.2-µm-wide, and 5-nm-thick graphene cantilever beam. For all the cantilever-based logic gates, the switching speed is 45 ns. The simulated cantilever-based logic gates could enable the implementation of different digital circuits.

LogIO: An Adaptive Gamification Learning Approach on Digital Logic Gates

The gamified e-learning approach has been widely used as a learning and teaching strategy, particularly in higher education. This strategy has been successfully used to engage, motivate and enhance learning performances. However, learners or students react differently to game designs and game mechanics depending on the subject area that a particular gamified application though there are several studies shows that gamification enhances motivation. In this paper, we designed and implemented a specific learning model for the gamified digital logic gates or LogIO. Thus, thirty (30) learners evaluated and we determined how do game design elements affect learners in terms of motivation, performance and learning experience. The main results of this study showed that learners agreed that the motivation level and usability of LogIO have a weighted mean of 4.56 and 4.49 respectively while performance and learning experience level has 81% during the utilization of the gamified mobile application. These results support the significance and relevance of adapting particular design elements for gamified digital logic gates to enhance motivation, performance and learning experience.

Realization of Various Gate level Combinational Circuits using Reversible Fredkin Gate

This paper presents the digital logic gates which are reconstructed using fredkin gate [1]. The advantage of basic fredkin gate is that we could save the thermal waste which comes out due to computation that causes heat as bits just disappear into loss of energy. Such computation won't need any energy input. These assumptions make the gates sound like an energy efficient solution. However the implementation is done at level of logic gates. This can further be used in sequential circuits to increase the life time of transmitter and receiver circuitry of nodes. It will make the transmission and aggregation of information at node very energy efficient. The drawback of this application is it will cost fare amount of time to process data. These technical hurdles will increase latencies at node level. The protocols infused with energy optimization methods and reversible logic gates offered noticeable improvements in achieving performance and ensuring security of data and graphics. Since the 1980s, with work of Fredkin [1], the reversible circuits have been used in building large scale integration of circuits as elementary units of mobile computing, and recently in wireless networks, drug designing and ultra-fast computing technologies [4].

On the design and analysis of a compact array with 1T1R RRAM memory element

In this paper, an analysis of a Verilog-A memristor model is discussed in order to be implemented in a 1T1R cell by exploring the characterization data of an OxRRAM device. The proposed analysis is done using mathematical formulation and verified by Spectre circuit simulator. The analysis is tested for a digital logic gate such as NAND gate for both, SET and RESET processes to perform read and write operations. Moreover, we explore diverse types of memory cells, two configurations are considered as a PROM and an EEPROM. Additionally, the implementation of the Verilog-A model on a crossbar array is discussed in details in terms of switching speed and the range of resistance. A comparison between the performances of various existing memory cells is also discussed. Our simulation results carry the desired nonlinear memristor fingerprint, the applicability to fit different switching behaviors. These results are verified by both electrical and experimental characterization data. We conclude that the proposed Verilog-A model is suitable for digitals circuits, crossbar arrays, low-power and high-density applications at the industrial levels.

An On-Chip Digital Monostable Multivibrator Using Inverter-based Delay Chains

Monostable multivibrator or one-shot timer is widely used in signal processing. In this paper, a simple and useful way to realize retriggerable monostable multivibrator by using digital logic gates is presented. The basic circuit is composed of one D flip-flop, one NAND gate, one inverter (INV) and two inverter-based delay chains. The width of the output pulse is adjusted through tuning the delay of the inverter-based delay chain. The retriggerable characteristic is realized by resetting all the delayed signals when new triggering occurs in the current monostable period. The basic circuit is designed and fabricated on-chip using a 180[Formula: see text]nm standard CMOS process with effective area less than 1200[Formula: see text][Formula: see text]m2. The retriggerable version is realized in a FPGA platform. Both simulated and measured results are in agreement with the theoretical analysis.

Digital logic for soft devices

Although soft devices (grippers, actuators, and elementary robots) are rapidly becoming an integral part of the broad field of robotics, autonomy for completely soft devices has only begun to be developed. Adaptation of conventional systems of control to soft devices requires hard valves and electronic controls. This paper describes completely soft pneumatic digital logic gates having a physical scale appropriate for use with current (macroscopic) soft actuators. Each digital logic gate utilizes a single bistable valve-the pneumatic equivalent of a Schmitt trigger-which relies on the snap-through instability of a hemispherical membrane to kink internal tubes and operates with binary high/low input and output pressures. Soft, pneumatic NOT, AND, and OR digital logic gates-which generate known pneumatic outputs as a function of one, or multiple, pneumatic inputs-allow fabrication of digital logic circuits for a set-reset latch, two-bit shift register, leading-edge detector, digital-to-analog converter (DAC), and toggle switch. The DAC and toggle switch, in turn, can control and power a soft actuator (demonstrated using a pneu-net gripper). These macroscale soft digital logic gates are scalable to high volumes of airflow, do not consume power at steady state, and can be reconfigured to achieve multiple functionalities from a single design (including configurations that receive inputs from the environment and from human users). This work represents a step toward a strategy to develop autonomous control-one not involving an electronic interface or hard components-for soft devices.

Design of ASIC Square Calculator Using AncientVedic Mathematics

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.