Digital Down Converter Research Articles

A multi-frequency EIT system design based on telecommunication signal processors

A multi-frequency electrical impedance tomography system for cardiopulmonary monitoring has been designed with specialized digital signal processors developed primarily for the telecommunications sector. The system consists of two modules: a scan-head and a base-station. The scan-head, located close to the patient's torso, contains front-end circuits for measuring transfer impedance with a 16-electrode array. The base-station, placed at the bedside, comprises 16 direct digital synthesizers, 32 digital down-converters, digital circuits to control the data acquisition sequence and a USB-2.0 microcontroller. At every step of the scan sequence, the system simultaneously measures four complex variables at eight frequencies. These variables are the potential difference between the selected pair of sense electrodes, the currents applied by the source and sink electrodes, and the current flowing through the ground electrode. Frequencies are programmable from 10 kHz to 2 MHz with a resolution of 2 mHz. Characterization tests were performed with a precision mesh phantom connected to the scan-head. For a 5 Hz frame rate, the mean signal-to-noise ratio and accuracy are, respectively, 43 dB and 95.4% for eight frequencies logarithmically spaced from 70 to 950 kHz. In vitro and in vivo time-difference images have been reconstructed.

Monobit Subsampler for Digital Downconversion in Pulse-Doppler Radar Applications

This paper introduces a monobit RF subsampling technique for digital downconversion in pulse-Doppler radar systems. Design considerations for this application include the level of quantization imbalance given a noise-only input, the relation between input and output signal-to-noise ratio (SNR), the affect of jitter over the complete dynamic range of operation, and sensitivity to intermodulation distortion. An RF integrated circuit is designed to demonstrate the monobit subsampling approach. Measured results show excellent agreement with theoretical predictions. The device can detect a 495-MHz signal at input SNR levels less than -30 dB using a 1-MHz sampling clock. Excellent performance is maintained even in severe timing environments showing more than 400 ps of rms clock jitter.

Design of programmable digital down converter for WiMAX

Design of a programmable digital down converter (DDC) has been proposed, which can be used in digital receivers that meets IEEE 802.16d/e (WiMAX) standard in wireless communication system. The design is based on the idea of software radio technology and the theorem of multi-rate signal processing, It can be implemented on FPGAs and can replace traditional ASICbased digital down converters in high channel count Software-Defined Radios.

Design of Programmable Digital down Converter for Wimax

Design of a programmable digital down converter (DDC) has been proposed, which can be used in digital receivers that meets IEEE 802.16d/e (WiMAX) standard in wireless communication system. The design is based on the idea of software radio technology and the theorem of multi-rate signal processing, It can be implemented on FPGAs and can replace traditional ASICbased digital down converters in high channel count Software-Defined Radios.

Wideband Digital Downconverters for Synthetic Instrumentation

In this paper, we introduce a new wideband digital downconverter (WDDC) for synthetic instruments (SIs). DDCs first tune to a signal's center frequency using a numerically controlled oscillator and mixer and then zoom-in to the bandwidth of interest using sample rate conversion (SRC). The SRC is required to produce continuously variable output sample rates from a fixed input sample rate over a large range. Current implementations accomplish this using a prefilter, an arbitrary factor resampler, and integer decimation filters. In this paper, we simplify the SRC of the WDDC, yielding a reduction in computational cost by a factor of 3 or more.

Design and implementation of high frequency ultrasound pulsed-wave Doppler using FPGA

The development of a field-programmable gate array (FPGA)-based pulsed-wave Doppler processing approach in pure digital domain is reported in this paper. After the ultrasound signals are digitized, directional Doppler frequency shifts are obtained with a digital-down converter followed by a low-pass filter. A Doppler spectrum is then calculated using the complex fast Fourier transform core inside the FPGA. In this approach, a pulsed-wave Doppler implementation core with reconfigurable and real-time processing capability is achieved.

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency.

Design and Implementation of DDC Based on Walsh Transform for HF Radar Receiver

This paper studies the design and multiplierless realization of a digital down converter (DDC) in a high frequency (HF) radar receiver. The novel structure mainly consists of a fast Walsh transform (FWT) and an inverse fast Walsh transform (IFWT), both of which can be implemented using only addition and subtraction. Because the transform kernels of the FWT and the IFWT are the same, the implementation complexity of the DDC is significantly reduced. Simulation and field test results are given to demonstrate that the proposed method outperforms the common method and is suited for real-time signal processing of software digital down conversion in a digital signal processor (DSP), such as the ADSP21060.

Application of undersampling technique for the design of an NMR signals digital receiver

In this article, undersampling technique theory and design, realization, and workbench test of a low-cost digital MRI (magnetic resonance imaging) receiver are re- ported. The authors first discuss classic analog receiver architecture, reporting its disad- vantages, and then present a receiver with a complete description of the electronic circuit. The intended use of the subsystem should be as a radiofrequency (RF) receiver chain in a low-cost dedicated MRI scanner (e.g., suitable for musculoskeletal limbs studies). The digital receiver consists of a passband (antialiasing) filter, an ADC (analog to digital converter) to digitalize the signal with the undersampling technique, and a DDC (digital down converter) for the frequency translation and filtering to process the signal using a PC. The use of the DDC guarantees perfect signals quadrature and high-performance filtering; moreover, it is adaptable to each modification of the system because of its programmabil- ity. Detailed specifications and hardware design of the digital receiver that is designed to be used in a dedicated MR scanner is provided, guaranteeing top performance and low cost. © 2006 Wiley Periodicals, Inc. Concepts Magn Reson Part B (Magn Reson Engineering) 29B: 107-114, 2006

Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme

Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration.

Superconductor Digital Receiver Components

We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of /spl pi//512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.

Adaptive antennas: the calibration problem

Adaptive antennas are recognized as a means of increasing the performance of communications systems. However, practical realization of such systems relies on suitable calibration of distortion effects caused by the circuitry and antenna structures. This work presents a detailed analysis of the classes of distortion that degrade the performance of adaptive antennas. This uses the results of an adaptive antenna testbed employing an eight-element circular array to illustrate the impact of temperature on performance. Design techniques that aid calibration are then described. In particular, digital downconversion, array design, harmonic sampling, sample clock dither, and clock management are discussed as a means of designing an adaptive array with the calibration problem in mind.

Implementation and experimental results of a three-transmitter three-receiver OFDM/BLAST testbed

A three-transmitter three-receiver orthogonal frequency-division multiplexing Bell Laboratories layered space-time testbed is set up, which achieves a peak data rate of 281.25 Mb/s and a spectral efficiency of 14.4 b/Hz/s. The transmitter of the testbed consists of three signal generators transmitting three independent OFDM signals at 25 Msamples/s synchronously. Three synchronized receiving links are used, each of which includes an RF receiver, an analog-to-digital converter, a digital downconverter, and a PowerPC processor for baseband processing. The performance and complexity of three typical BLAST detection techniques (linear detection, ordered decision feedback detection, and partial decision detection) are evaluated and compared using the data from the experiments conducted in both line-of-sight and non-line-of-sight indoor environments.

CIC filter theory in DDC and implementation by using FPGA

Cascade Integrator Comb(CIC) filter is the main part of the next generation High Frequency (HF) radar. This paper describes the key points of CIC theory in the Digital Down Conversion (DDC) module of a radar receiver, and takes advantage of the high flexibility and high density feature of Field Programmable Gate Array (FPGA) for putting forth to design the CIC filter by using FPGA. This paper provides particular insight into design by FPGA, which has advantages in high speed operation and simply structure. Some important and practical applications are given in this paper. The simulation result proves the validity and veracity. Because we can adjust the parameters freely according to our need, the CIC filter can be adapted to the next generation HF radar.

Multiplier-Free Bandpass Channelizer for Undersampled Applications

Today, there is a strong motivation to increase the digital content of low-power wireless transceivers. Direct data conversion is often not possible, or practical, at high radio frequencies. In such instances, undersampling analog-to-digital converters (ADCs) are often used to alias information, residing above the ADC's Nyquist frequency, down to baseband as a set of nonoverlapping subbands. In this paper a low-complexity, programmable, band-selectable channelizer (a.k.a., digital downconverter) is presented that can efficiently access specific subbands from an undersampled signal space.

A modular data and control system to improve sensitivity, selectivity, speed of analysis, ease of use, and transient duration in an external source FTICR-MS

We present here a new Fourier transform ion cyclotron resonance mass spectrometry (FTICR-MS) controller designed and constructed to meet the growing need for increased speed, memory, and ease of use. The system realizes these goals via the first published application of fast PXI bus technology and by employing a graphical user interface (GUI) for control of all aspects of ion production, delivery, containment, manipulation of internal and kinetic energies, and measurement in an external source instrument. Additionally, new hardware for monitoring and control of these aspects and for processing extended datasets both to and from the instrument have been implemented. The modular nature of the control hardware makes the instrument platform, in this case a modified external source 7T FTICR-MS, irrelevant. The GUI consists of two separate modules; one provides a temporal representation of the pulses, voltages (rf and dc), and dc heater currents that control all aspects of the experiment while the other provides complex data analysis capabilities and design of excitation waveforms. Real-time monitoring of the transient signal is available in this module as well as near real-time monitoring of the resulting mass spectrum (using a truncated dataset). A PXI bus with 40 digital to analog converters (DAC) and 64 digital (TTL) sources drive the source, optics, and trapping functions of the instrument as well as the other peripheral hardware. Acquisition is realized using a VME bus with a TTL triggered program resident on an embedded processor to minimize dead time. The acquisition system is equipped with 192 MB memory for both excitation and detection waveforms with FIFO buffering to provide full rate bandwidth of 10 MHz, and four digital down converters (DDCs) to enable mixing of heterodyne signals for narrow band measurements completes the ensemble.

An efficient implementation architecture for wide-band digital downconversion

The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.

A DSP-based DS-CDMA multiuser receiver employing partial parallel interference cancellation

The implementation of advanced DS-CDMA receivers based on multiuser detection principles is becoming a reality thanks to the combination of an improved understanding of the theoretical basis of multiuser detection and advances in digital, mixed-signal, and RF technologies. Due to their lower complexity, subtractive interference cancellation approaches are attractive for the practical implementation of multiuser detection. In a parallel interference cancellation receiver, it is practical to use the soft outputs of a matched filter bank for amplitude estimation. A bias arises in the decision statistics, however, due to imperfect estimation and interference cancellation. In this paper, the source of the bias is explicitly recognized, and a partial interference cancellation scheme that mitigates the negative effects of biased estimation and significantly improves system performance is proposed. A practical real-time algorithm that significantly reduces the implementation complexity of this scheme without sacrificing performance is then derived. To facilitate a software radio implementation, the signal processing complexity of the approach is characterized. The real-time processing algorithm is tested via implementation in software on a floating-point general-purpose DSP. The prototype includes a flexible software-based architecture which performs IF sampling and uses digital downconversion prior to baseband processing. The hardware test setup is described, and the results are presented and compared with simulation and analytical results. The experimental results confirm the simulation and analytical results which show large performance gains over the conventional matched filter.

Low-power multirate architecture for IF digital frequency down converter

In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-IF oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on the multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. The design example shows that it consumes only 24% of the power of the direct implementation while occupying 26% less area.

Data-adaptive digital video format conversion algorithms

With the emergence of advanced display media as well as digital video coding and compression schemes came a variety of new video formats including program content dependent formats, as proposed by the Grand Alliance for their high definition television (HDTV) standard. Digital video down-conversion is a low complexity quality reduction task, whereas the more complex video up-conversion incorporates a tradeoff between computational cost and perceptual quality. Motion-compensated conversion algorithms have the potential for good results, but go in hand with a computational complexity disadvantage, whereas motion-adaptive interpolation methods constitute a compromise between the extremes. This paper presents a general motion-adaptive format conversion approach based on a multiresolution decomposition and nonlinear subband interpolation filtering. The class of Ll permutation filters feature a flexible, input-signal dependent behavior by exploiting the order statistics of an input signal. In this paper, such an approach is utilized for interpolation purposes, applicable to any arbitrary format conversion problem. A successful application of Ll filter based interpolators in combination with a hierarchical multiresolution decomposition as a motion-adaptive format conversion method is presented. As an evaluation of performance, two format conversion case studies are presented, namely deinterlacing for progressive display media and frame-rate up-conversion for the reduction of temporal artifacts.