Digitally Controlled Oscillator Research Articles

Analysis and Design of Digital Controlled Low-Phase-Noise CMOS LC_VCO

A fully integrated cross-coupled digital controlled LC tank voltage-controlled oscillator (LC-VCO) is proposed to achieve a low phase noise, the LC_VCO receives the external n-bits control words FTRIM to control the capacitors switches and change LC-tank shunt capacitors, thus changes the tuning range of LC_VCO. Meanwhile the LC_VCO receives the external k-bits control words KVCO to control the varactors switches and led to the change of voltage control sensitivity. The digital controlled oscillator based on the proposed topology is simulated and verified by the standard SMIC 0.13um CMOS technology. The simulation gave a phase noise of -125.3dBc/Hz at 1 MHz, the entire circuit consumes the current is only 2.98mA under a 1.2 V supply.

A high-accuracy DCO with hybrid architecture**Project supported by the National Natural Science Foundation of China (Nos. 61306025, 61474135).

In this paper, a novel hybrid digital-controlled oscillator (DCO) is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts: DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature (PVT) variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm2 chip area. The output frequency is adjusted from 15–120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6–1.8 V supply voltage and 0–80 °C temperature variations in TT, FF, SS corners.

20-Mb/s GFSK Modulator Based on 3.6-GHz Hybrid PLL With 3-b DCO Nonlinearity Calibration and Independent Delay Mismatch Control

A hybrid two-point modulator which mitigates the nonlinearity problem of a digitally controlled oscillator (DCO) and provides a fine delay mismatch calibration is proposed for high data rate applications. A DCO with a separate high-pass modulation path in which only 3 b are used for a capacitor array is designed for flexible gain partition and simple nonlinearity calibration. A nonuniform multilevel quantizer and a finite-impulse response filter are employed to improve modulation quality and reduce quantization noise for high data rate. In the low-pass modulation, a fractional- ${N}$ divider based on a phase rotator and an additional high-frequency $\Delta \Sigma $ modulator enables fine delay time control between two modulation paths. Delay mismatch calibration circuit based on a time-to-digital converter is designed to calculate the optimum delay time automatically. A prototype 3.6-GHz two-point modulator is implemented in 65-nm CMOS. The modulator performs 20-Mb/s GFSK with the error vector magnitude performance of 3.7%, consuming 10.6 mW from a 1-V supply.

Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder

An exponentially scaling C-2C switched-capacitor (SC) ladder is proposed for millimeter-wave digitally controlled oscillators (DCOs) to achieve high-frequency resolution with small chip area. The 65-nm-CMOS DCO prototype measures a frequency resolution of 4 Hz over a frequency range of 14.2%, from 54.79 to 63.16 GHz, with a phase noise at 1-MHz frequency offset of −90.7 to −94.1 dBc/Hz while consuming 18 mW, corresponding to an FOM $_{T}$ from −176.6 to −180 dB. The DCO occupies a core area of 0.10 mm2, with only 0.012 mm2 for the C-2C SC ladder.

A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) $P_{\mathrm {out}}$

This paper describes a sub-1-V 2.4-GHz ZigBee transmitter (TX) with scalable output power ( $P_{\mathrm {out}}$ ) and system efficiency. It features a function-reuse class-F topology unifying the digital-controlled oscillator (DCO) and power amplifier (PA), designated as DCO-PA. Unlike the existing current-reuse topologies that rely on transistor stacking, here the power consumption of the DCO and PA-driver is absorbed into the DCO-PA without losing the voltage headroom, while allowing a low supply voltage. The DCO-PA also benefits from a six-port transformer with customized coupling coefficients and turn ratios to jointly perform the functions of resonant tank and output matching network, saving the chip area. A fractional-N all-digital phase-locked loop (ADPLL) realizes a two-point data modulation. Its phase-interpolated time-to-digital converter prevents time-consuming calibration. The entire TX fabricated in 65-nm CMOS occupies a 0.39-mm $^{\mathrm { {2}}}$ active area. The standalone DCO-PA shows a peak efficiency of 26.2% at a 6-dBm $P_{\mathrm {out}}$ , and a back-off efficiency of 17.7% at a −4.3 dBm $P_{\mathrm {out}}$ under a scalable supply voltage (0.3–0.7 V). The system efficiency, including the ADPLL, is 22.6% (14.5%) at 6-dBm (0-dBm) $P_{\mathrm {out}}$ . The HS-OQPSK modulated output complies with the ZigBee spectral mask with an adequate margin and the error vector magnitude is 2.29%.

Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback

This paper proposes a time-residue feedback scheme to balance resolution and complexity in a cell-based time-to-digital converter (TDC). The time residue is amplified and fed back into a cyclic-ring Vernier recursively until it cannot be detected correctly. Only one variable-resolution cyclic-ring Vernier and one tunable delay-chain time amplifier (TA) are adopted. Both coarse and fine oscillators of the proposed Vernier which are designed by the same variable-resolution digital controlled oscillator can be switched off to decrease ground bounce during TA activities. With various control codes, the TDC resolution is also programmable. The test application-specified integrated circuit which has a 13-b resolution and occupies 0.02 mm2 in TSMC 65-nm CMOS process can operate in either feedback or feedforward mode. In feedback mode, the measurements of sampling rate, resolution, input range, differential nonlinearity, and integral nonlinearity are 10 MHz, 0.98 ps, 5.76 ns, ± 0.8 LSB, and ± 2.2 LSB, respectively; it also consumes 3 mW at 1 V supply voltage. The sampling rate, resolution, and power dissipation of the feedforward operation are 250 MHz, 6.01 ps, and 17.5 mW, respectively.

A frame-based EM-simulation for design ofLCoscillator with MoM capacitor banks

This article presents a simulation method for the design of a digitally controlled oscillator (DCO). Electromagnetic (EM) simulations are essential and inevitable for modern LC oscillator design. Although EM-simulators provide high accuracy, the EM-simulation time is very long when metal-oxide-metal (MoM) capacitors are present. The proposed frame-based EM-simulation can significantly reduce the EM-simulation time even in the presence of MoM capacitors without influencing the accuracy. To verify the proposed method, a DCO was fabricated using a 55-nm CMOS process. Measurements of the DCO are in good agreement with the frame-based post-layout simulation results. In addition, the DCO has good performances with a low power consumption of approximately 0.68 mW.

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Low 1/ $f$ DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (~10 Gsamples/s) with intermediate frequency placed beyond 1/ $f$ noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE.

A 0.2–1.45-GHz Subsampling Fractional- $N$ Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection

A digital fractional-N subsampling multiplying delay-locked loop is proposed in this paper. A zero phase-offset latch-based aperture phase detector is introduced in a reference spur cancellation loop to precisely cancel any static phase offset (SPO) between the injected reference and the digitally controlled oscillator (DCO) phases. An in situ detection scheme is employed to directly measure this phase offset accurately by obviating the requirement of a high-speed off-chip measurement setup. Moreover, a mathematical expression is derived for the calculation of reference spur generated from a given SPO. A uniformly distributed switched capacitor-based DCO frequency tuning achieves highly linear gain. The chip prototype is fabricated in a 1.2-V supply, 65-nm LP CMOS technology and covers an output frequency range of 0.2-1.45 GHz while occupying a core area of 0.054 mm 2 . Measured phase noise at 1.4175 GHz is -95 dBc/Hz at 100-kHz offset, which is 9 dB lower than in phase-locked loop mode of operation.

Coupling-Shielded Inductor for High Isolation Between PA and <italic>LC</italic>-Based DCO

This letter presents a novel coupling-shielded inductor. The inductor has a magnetic coupling shield ring (CSR), designed with an Al pad metal. The CSR has an electromotive force-induced current, which flows in such a direction as to oppose the magnetic field from an aggressor. As a result, the proposed inductor can be protected from the attack of a power amplifier (PA) with a strong magnetic field. The inductor is applied in an $LC$ -based digitally controlled oscillator (DCO) to verify the enhancement of isolation. It was fabricated by a 55-nm 1P6M CMOS process. Using the CSR, the isolation between the DCO and PA is increased by about 11 dB without degradation of the DCO performance. The DCO with CSR has a low phase noise of −114.5 dBc/Hz at 1 MHz with 0.74-mW power consumption.

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network

A digital clock and data recovery (CDR) is presented, which employs a low supply sensitivity scheme for a digitally controlled oscillator (DCO). A coupling network comprising capacitors, resistors, and coupling buffers enhances the supply variation immunity of the DCO and mitigates the jitter performance degradation. A supply variation-dependent bias generator produces the corresponding bias voltage to alleviate the supply variation with minimal area and power penalty. The proposed scheme improves 29.3 ps of peak-to-peak jitter and 11.5 dB of spur level, at 6 and 5 MHz 50 mVpp sinusoidal supply noise tone, respectively. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER $ for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm2.

A Time-to-Digital Converter Based on a Digitally Controlled Oscillator

Time measurements play a crucial role in trigger and data acquisition systems of high-energy physics experiments, where synchronization between system elements, signal calibration, and phase-measurement accuracy is often required. In this paper, we present a fully digital time-to-digital converter (TDC) architecture and its application, based on a synthesizable digitally controlled oscillator (DCO), where the TDC is used to measure the phase relationship between a timing signal and a 40-MHz reference clock. The DCO design is technology independent; it is described by means of a hardware description language and it can be placed and routed with automatic tools. The TDC will be used in the new readout chip that is under development for the muon detector electronic upgrade in Large Hadron Collider beauty experiment at CERN. The TDC presented in this paper has the fundamental task of measuring, with a resolution of about 1.5 ns, the phase difference between the 40-MHz LHC machine clock and a digital signal coming from the muon detector.

An all‐digital phase‐locked‐loop with a robustness enhanced dual‐mode DCO

ABSTRACTAn all‐digital‐phase‐locked‐loop (ADPLL) with a dual‐mode Class‐A/Class‐C Digital‐controlled‐oscillator (DCO) is presented in this letter. During the start‐up phase, the DCO operates in the Class‐A mode with increasing tail current. A low‐power amplitude‐to‐pulse‐converter (APC) is proposed to detect the oscillating amplitude of the DCO. After the start‐up, the DCO switches to the Class‐C mode with reduced tail current, resulting in better phase noise and lower power consumption. The ADPLL with the proposed DCO is implemented in a 65‐nm CMOS technology. The Class‐C mode DCO exhibits a phase noise of −123.3 dBc/Hz at 1‐MHz offset with a 2.7‐GHz carrier frequency. Measured results show about a 2.9‐dB phase noise improvement at 1‐MHz offset among the tuning range of 2.5–2.9 GHz, compared to the Class‐A DCO under the same power consumption. The figure‐of‐merit (FOM) and FOM including the tuning range (FOMT) of the DCO is 188.7 and 192.1, respectively. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:312–315, 2017

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

This paper presents a fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A $\Delta \Sigma $ -less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.

A 5-mW, 1.2–3.5-GHz Capacitive Degeneration in LC-Digitally-Controlled Oscillator for Nano-Satellite Frequency Synthesizers in 90-nm CMOS

This paper proposes an 8-bit LC tuned digitally-controlled oscillator (DCO) that exploits a new tunable active inductor (TAI) with a high [Formula: see text]-factor. This TAI achieves a maximum [Formula: see text]-factor value of 98 over a frequency range of 1770[Formula: see text]MHz. It tunes from 3.55[Formula: see text]nH to 15.2[Formula: see text]nH. The proposed TAI is used in the resonator of a wide tunable low-phase-noise DCO-LC oscillator. The tuning circuitry of the DCO with an additional resistance contributes to better effective capacitance characteristics as compared to the basic topology. Thanks to the capacitive degeneration network formed by a resistance connected in parallel with a capacity, the achieved frequency resolution is between 3[Formula: see text]kHz and 16[Formula: see text]kHz without any dithering. The proposed DCO with capacitive degeneration oscillates at a frequency that can be tuned from 1.22 to 3.52[Formula: see text]GHz with 65% tuning range. It consumes 5.2-mA current from a 1.0-V voltage supply, achieves a phase noise of [Formula: see text]105.8[Formula: see text]dBc/Hz at 1-MHz offset and exhibits a figure of merit (FoM) of [Formula: see text]178[Formula: see text]dBc/Hz. The proposed digitally-controlled oscillator was implemented in TSMC 90-nm CMOS MS/RF technology.

1.45 GHz differential dual band ring based digitally-controlled oscillator with a reconfigurable delay element in 0.18 μm CMOS process

This paper presents a dual band Digitally-Controlled-Oscillator (DCO) based on Ring-Oscillators (RO) topology with differential input/output at 1.45 GHz is proposed. The circuit has two frequency band which switches by a digital mode bit. Switching between two bands of DCO, will change delay path and power consumption during the run time. A new Source-Coupled-Logic (SCL) based reconfigurable delay element with Schmitt-Trigger (ST) characteristic is used in each stage and 6 bits digital code control their current tails. Power consumption profile with frequency in each band has a steady regime. The proposed designs are fully differential, which is appropriate for low jitter high performance applications. The proposed DCO is simulated by spice with CMOS standard 0.18 µm @ 1.8 v supply. The frequency, power consumption and jitter in lower band are 455.2 MHz to 505.1 MHz, 1.98 mW (at 455 MHz), 6.04 ps (at 505.1 MHz) and for upper band are from 1.39 MHz to 1.45 MHz, 9.7 mW (at 1.39 GHz) and 3.48 ps (at 1.45 MHz), sequentially. In this paper also circuit analysis of proposed DCO, delay calculation and comparison and analytical equation for frequency bands are obtained. Also, Monte Carlo and PVT test shows acceptable frequency tolerance.

A new local clock generator for globally asynchronous locally synchronous MPSoCs

The evolution of technology into deep sub-micron domains leads to increasingly complex timing closure problems to design multiprocessor systems. One natural alternative is to resort to the globally asynchronous, locally synchronous paradigm. This work proposes a generic architecture for very low power- and area-overhead local clock generators (LCGs) to drive processors, network-on-chip routers and other intellectual properties (IPs). As one original contribution, the article details the design of a digitally controlled oscillator (DCO) which is the core of the LCG architecture. This DCO was designed using a CMOS 65 nm technology. It produces at least 16 distinct frequencies from 117 MHz to 1 GHz and supports clock gating and glitch-free frequency changes. The DCO design is robust to process, voltage and temperature variations, takes 850.6 µm2 and dissipates up to 197 µW. The article also proposes an LCG controller to improve frequency accuracy for IPs which require more accurate timing. Designed in the same technology, the controller takes 2250 µm2 and consumes 130 µW in typical conditions, or 160 µW, under worst-case conditions.

A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme

This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient-based adaptive single-tone spur cancellation scheme. By using the injection-locked ring oscillator, the TDC quantization step is automatically tracked with the period of the digitally controlled oscillator (DCO) over PVT, and hence is free of calibration. The multi-phase TDC further achieves a fine resolution of 7 to 12 ps, depending on the DPLL's operating frequency. The proposed single-tone spur cancellation scheme achieves more than 40 dB spur suppression. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS technology and synthesizes frequencies from 2.7 to 4.8 GHz with a 1V supply, consuming 21.2 mW. The measured in-band phase noise is −92 dBc/Hz at 40 kHz offset, the far out phase noise is −130 dBc/Hz at 3 MHz offset, with a reference spur of −86.5 dBc.

A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation

A digital-to-frequency converter (DFC) assisted by a built-in-self-measurement mechanism is presented. It demonstrates the capability to overcome oscillator pulling that is caused by the high-speed digital frequency-tuning signal that is fed into the DFC's digitally-controlled-oscillator (DCO), thereby allowing the DFC to accommodate high-rate modulating data. Thus, by placing replica images and quantization noise far away from the transmitted carrier, the presented DFC is suitable for wireless applications having the most demanding spectral mask requirements, without necessitating RF filtering in the transmitter's signal path. The proposed solution, designed with minimum overhead, reduces the extent of injection pulling experienced by the digitally controlled oscillator (DCO) due to ΣΔ dithering applied to its capacitor bank by adjusting the phase between the aggressor and victim signals through a digitally controlled delay (DCD) line. The proposed calibration and compensation scheme for the DCD is autonomous and simple computationally. The proposed solution has been demonstrated in a transmitter of a commercial cellular CMOS system-on-chip (SoC).

A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply.